摘要
摘要
随着半导体工艺的发展，工艺尺寸不断缩小，芯片集成度越来越高，同时EDA 工具的自动化设计能力也快速提升，因此芯片功能更加强大复杂。与之对应，其验证的复杂度也相应增大，传统的验证方式已经很难满足当前验证工作需要。本文介绍并使用了UVM（Universal Verification Methodology）来解决此难题，它继承了VMM和OVM的优点，是业界目前最流行最先进的标准化验证方法学。UVM验证方法学是使用SystemVerilog语言这一面向对象编程语言的方法学，同时能够保证与硬件描述语言的兼容性。
本文主要工作内容是分析实习项目中的Power架构传感器信号处理模块的所有功能点并搭建相应的UVM验证平台。该模块所需验证的功能包括温度或者电压模式下传感器串行信号的获取、与PCB总线的交互协议、温度或者电压警告信号的产生以及强制产生、对传感器写入配置信息、时间检测传感器的配置、时间检测传感器数据的输出、时间戳、扫描链与初始化。这些工作模式是由32位地址线，64位数据线，1位读写标志位以及它们各自的奇偶校验位控制。同时本模块还有请求的已知位和有效位、回复的已知位和有效位、端口重置位共同来控制总线的信息交互规则。由于上述数据位的组合十分复杂，存在众多感兴趣的验证边界，所以本文首先制定了对应的验证计划，包括功能覆盖率模型、断言覆盖率模型、包约束模型，然后应用UVM众多内建机制来保证后续仿真验证的全面、正确。
为了实现本次验证工作的要求与平台的重载、复用，该UVM验证平台建立中采用了多种UVM内建机制包括virtual quence机制、寄存器模型、factory机制、callback 机制、config_db机制等。UVM验证平台本质上是其验证语言SystemVerilog的拓展库，所以还沿用了其虚拟端口、断言、覆盖组、受约束随机化等多种独特功能。通过这些机制的应用，本文的验证平台按照所需的PCB总线信号时序自动化地产生了大量感兴趣的随机激励，针对扫描链的初始化，还利用factory机制产生了9个测试用例。
按照需要搭建完成本文的UVM验证平台并建立66个断言、14个覆盖组后，便可使用NCSIM仿真得到仿真信息文件和覆盖率报告，并使用vManager分析覆盖率报告。通过与技术文档对比，得到断言、功能覆盖率收敛于100%、代码覆盖率达到95%、log仿真文件无错误。最终证明了UVM验证方法在灵活性、重用性、缩短验证周期上的优势且不会损失验证全面性与正确性。
关键词：UVM，SystemVerilog，传感器信号处理模块，断言，功能覆盖率
ABSTRACT
ABSTRACT
With the development of miconductor technology, the integration is getting higher and higher,the capability of integrated circuit design is also rising rapidly, so the scale of the integrated circuit is mor
e powerful and complex. As the result，The complexity of its verification has incread, and the traditional verification method is difficult to meet the current situation. This article describes the UVM (Universal Verification Methodology) to solve this problem, which inherits the advantages of VMM and OVM。Now it has become the most popular and most advanced standardized method of verification. The UVM is an object-oriented programming methodology which us the SystemVerilog language, while ensuring compatibility with the hardware description language.
The main work of this paper is to analysis the function of the Power Sensor Signal Processing Module and build the UVM verification platform for it. The module which required to verify includes its nsor rial signal identification in therm or voltage mode, the interaction with PCB bus, the forced or not forced generation of temperature or voltage warning signal, writing the nsor configuration information, Time Detection nsor configuration information, Time Detection nsor data output, timestam, scan chain and initialization. The modes are configured by 32-bit address lines, 64-bit data lines, 1-bit read and write flags with their parity bits. At the same time, there are acknowledge and valid bits for request and reply, and port ret bits to control the bus interaction is correct. As the combination of the above signals is very complex with a number of interesting verification boundaries, this thesis developed a corresponding verification plan firstly, including functi
浪子学画onal coverage model, asrtion coverage model, transaction level constraint generation and then apply many built-in UVM mechanism to ensure that the following simulation is comprehensive and correct.
For the functional verification requirements and platform reu，the UVM verification platform is built with the variety of UVM built-in mechanism, such as virtual quence mechanism, register model, factory mechanism, callback mechanism, config_db mechanism. The UVM is esntially an extension library for its verification language SystemVerilog, so it also continues to u a variety of unique components such as virtual interface, asrtion, covergroup, and constrained randomization. After completing the UVM verification
儿童手工飞机platform, you can get the simulation information file and coverage report by NCSIM and u vManager to analyze them.
According to the comparison between the results of asrtion, function coverage, error-free simulation information and the technical documents, it is proved that the UVM has the advantages of flexibility, reusability and shortening the verification period without losing the correctness and compre
hensiveness of verification while asrtion and function coverage converge to 100%.
Keywords: UVM，SystemVerilog，the Power Sensor Signal Processing Module，asrtion, function coverage
插图索引插图索引
UVM树形结构 (6)
UVM组件继承关系 (6)
Pha时序上的分类 (8)
Tpc_therm_wrap模块结构图 (13)
运行状态机 (14)
请求有效与请求已知 (16)
蒋卓君
回复有效与回复已知 (16)
准备采样控制信号 (20)
传感器数据输入 (20)
警告信号的产生 (21)
电压模式传感器与模块的交互 (22)
读传感器处理结果 (22)
老湿机看片传感器配置信息输出 (23)
警告注入模式下自动重置 (24)
重置采样计数器 (25)
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时钟选择配置与时钟检测工作状态配置 (25)
时钟检测传感器输出控制端口与其信息输入 (26)
时钟检测传感器检测信息输出到PCB总线 (26)
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工作计划 (30)
验证环境结构 (33)
Interface代码（a） (34)
Interface代码（b） (35)
pcb_q代码 (36)
body()任务代码 (37)
therm_vq代码 (38)
rsp_ack断言代码 (41)
func_scan_ena断言代码 (42)
ret_ifc_rsp断言代码 (42)
req_p断言代码 (43)
最小工作计算函数与断言代码 (45)
rial_datax_in断言代码 (46)
hold_sample断言代吗 (47)
inject_ena_warn断言代码 (48)
sleep_mode断言代码 (49)
rial_data_v断言代码 (50)
打乒乓球ret_sample断言代码 (51)
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约束代码 (52)
覆盖组代码 (57)
callback代码 (58)
断言触发 (59)
仿真报告 (59)
功能覆盖率报告 (60)
各个断言的覆盖率报告 (61)
整体覆盖率报告 (61)
