专利名称：Decision feedback equalization
发明人：Alan S. Fiedler
申请号：US14626783装订线怎么设置
申请日：20150219
公开号：US09455846B2
公开日：
20160927
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义无反顾专利附图：
春联模板摘要：A signal sampling system that includes N samplers is disclod. Each sampler includes a data input having a decision logic level threshold, a plurality of offt control inputs, a plurality of offt magnitude inputs, an un-buffered output, and a buffered output. Each sampler further includes circuitry coupled between the inputs and outputs
蒜蓉西兰花的家常做法that is configured to cau a time delay from an input signal transition to an output signal transition such that, after an offt control input transitions from a first voltage to a cond voltage, the decision logic level threshold changes in a time substantially less than one gate delay, and after the sample clock transitions from a first logic state to a cond logic state, the un-buffered output transitions within a time substantially equal to one gate delay and the buffered output transitions within a time substantially equal to two gate delays.
申请人：Microsoft Technology Licensing, LLC
地址：Redmond WA US
国籍：US
日薄西山
文学代理人：Gregg Wisdom,Judy Yee,Micky Minhas
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