马尔库塞J OURNAL OF I NFORMATION S CIENCE AND E NGINEERING 24, 115-127 (2008)
Short Paper_________________________________________________ An Effective Decap Inrtion Method Considering Power Supply Noi during Floorplanning*
爽快的近义词C HAO-H UNG L U, H UNG-M ING C HEN**AN
D C HIEN-N AN J IMMY L IU
Department of Electrical Engineering
National Central University
Taoyuan, 320 Taiwan
E-mail: {chlu; jimmy}@ee.ncu.edu.tw
**Department of Electronics Engineering and SoC Rearch Center
National Chiao Tung University
bjeeaHsinchu, 300 Taiwan
E-mail: u.edu.tw生物技术专业排名
As VLSI technology enters the nanometer era, the supply voltage is continually dropped. This condition helps to reduce the power dissipation, but make the power in-
tegrity problem become wor. Employing decoupling capacitances (decap) at floorplan
stage has been a common approach to alleviate the supply noi problem. However, the
decap budget is often overly estimated in previous rearches. Besides the decap budget
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computation, the available floorplan space does not fully ud in previous works. In one
floorplan, it usually has many available spaces except the empty space that could be ud
to inrt the decap without increasing the floorplan area. Therefore, our goal in this work
is to develop a better model to calculate the required decap to solve the power supply
noi problem of area-array bad designs and to increa he usage of the available space
in the floorplan to reduce the area overhead caud by decap inrtion. The experimental
results are encouraging. Compared with other approaches, our algorithm can reduce
52.6% decap budget on the MCNC benchmarks but still keep the power supply noi in
the given constraint. The final floorplan areas with decap are also less than the numbers
reported in previous papers.
猫薄荷Keywords: decoupling capacitance, floorplanning, physical design, power estimation,
area-array architecture
1. INTRODUCTION
As VLSI technology enters the nanometer era, the supply voltage is continually dropped. This condition helps to reduce the power dissipation, but also decrea the noi margin of the devices. Therefore, the integrity problem has become one of the major fac-tors that affect chip yield. Basically, the integrity problems can be categorized into the signal integrity problem and the power integrity problem. In this paper, we focus on the power integrity problem that caud by the power supply nois, such as the IR-drop and
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ΔI (delta-I , Ldi/dt) noi. Many rearches have propod various approaches to solve this problem at every design stages. The power/ground (P/G) network [4-8] is an impor-tant factor in the supply noi problem. The power supply noi can be greatly improved by a better P/G network and with minimal penalty cost. In [9, 10], the authors u opti-mal wire sizing to increa the integrity of the signals.
Besides sizing the power lines, employing decoupling capacitances (decap) has been a common approach to reduce the supply noi. Traditionally, the decap inrtion process is performed after ro
uting in the physical design flow. Unfortunately, the area of the de-cap is greatly incread becau the module placement has been fixed. Therefore, more and more rearches propo to inrt decap before routing. In [11], the authors propo a two-step decap inrtion method to improve power supply noi in placement level. This method includes one prediction method and one correction method. In the predic-tion step, the required decap is pessimistically estimated. Although the decap size can be adjusted in the correction step, it is still possible to obtain smaller area overhead if the decap inrtion can be considered at earlier stage.
In [1] and [2], the authors propo the decap inrtion methods at floorplan level to reduce supply noi. Unfortunately, the decap budget is often overly estimated in previ-ous rearches. They assume that the decap must be able to fully store the maximum cur-rent of the module, which is too pessimistic in our obrvation. Besides the decap budget computation, the available floorplan space does not fully ud in previous works. In one floorplan, it usually have many available spaces except the empty space that can be ud to inrt the decap without increasing the floorplan area. Therefore, our goal in this work is to develop a better model to calculate the required decap to solve the power supply noi problem and to increa the usage of the available space in the floorplan to reduce the area overhead caud by decap inrtion.
In recent high-performance IC manufacturing, the flip-chip and area-array architec-tures [18] are often ud. The traditional location of the I/O Pad is t around the core. In the area-array architecture, the I/O Pad is t over the core. Becau the I/O Pads are dis-tributed over the chip, the packaging issue should be considered in floorplan stage to reduce the distance from the core I/O to the signal bumps. In [12], the authors provide a power bump allocation method to effectively reduce the distance with from the supply voltage nodes to modules, thus reducing power supply noi. However, without decap inrtion, resultant floorplans may still suffer from supply noi violations.
Bad on the area-array architecture, we propo a two-step approach in this paper that includes a noi-driven floorplanning algorithm and a decap inrtion algorithm to suppress power supply noi at the floorplan level, as illustrated in Fig. 1. First, we u a noi-driven floorplan algorithm to reduce the possible noi. The power supply noi would be substantially incread when two high-current blocks are placed at the adjacent locations. Therefore, high current consumption blocks are not abutted in our floorplan algorithm.The cond step is the decap inrtion method. We u a Noi-driven Decap Planning with Minimum Area Inrtion (NDP_MAI) algorithm to reduce the noi after floorplanning. In this step, given an initial compacted floorplan and the current consump-tion for
all blocks, the NDP_MAI algorithm can calculate the minimal decap budget and determine the locations of the inrted decap for each block to satisfy the noi con-straints.
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Fig. 1. The illustration of our two-step approach.
The key contributions of this paper are summarized as follows: (1) We have devel-oped a better noi estimation model that can obtain less decap area compared with pre-vious approaches; (2) We u the O-tree reprentation with strong adjacent module rela-tion as our engine for noi-driven floorplanning, and successfully modify two opera-tions Delete and Inrt to avoid high-current blocks being placed at adjacent locations; (3) We have prented an algorithm to increa the usage of the available space in the floor-plan for the required decap to meet the noi constraint.
The rest of the paper is organized as follows. Section 2 prents the problem formu-lation. Section 3 describe our noi estimation method and decap budget computation. The floorplanning approach and decap inrtion algorithm are prented in ction 4. Experimental results are shown in ction 5. We conclude the paper in ction 6.
2. PROBLEM FORMULATION
In the traditional chip design, the decap inrtion method is ud to solve the power supply noi problem after the routing level. In this paper, we propo to solve this prob-lem in early design stage. Given a t of module, B 1, B 2, …, B m , k gen I and max ,k I of each block , of each block B i , the
locations for each VDD source and the noi constraint for each module, find a feasible solution such that each block B i obtains appropriate and minimal decap budget size DBSi , and minimum penalty area when DBSi is inrted.
3. ESTIMATING POWER NOISE AND REQUIRED DECOUPLING CAPACITANCE
3.1 Power Delivery Model and Noi Estimation
In this paper, the power source distribution is bad on the area-array architecture
[18]. The area-array architecture is a mesh structure and the VDD and GND bumps are uniformly distributed across the die with signal bumps in fixed intersperd location, as illustrated in Fig. 2 (A). In designing chips, the I/O locations will greatly improve the performance than the traditional design. If the area-array architecture is ud, the distance
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Fig. 2. Area-array footprint SoC.
from the core I/O to the connection point of the package would be substantially de-cread and the performance would be significantly improved. Therefore, the area-array architecture is extensively ud in high-performance chips.
In the general chip design, any VDD bump would supplies the current to all mod-ules according to the direct proportion of the distance from the bump to the module. In the area-array architecture, four neighboring VDD bumps (right-top, right-down, left-top and left-down) of the module would supply the main current. Therefore we compute the noi from the VDD bumps only. Becau the power network is a mesh grid, the VDD bumps would follow the grid to supply the current. If we compute the noi for each cur-rent path, we would expen great times to obtain the accurate result. In [2], it has an experimental result about the computation of the path. If we calculate the noi from four neighbor VDD bumps and consider the shortest paths and the cond shortest paths only, the error i
s less than 10% (compared with HSPICE). This computation method is fast and the error could be control in one expectable range. We u this method to compute the power supply noi in the floorplan level. We can u Kirchhoff’s voltage law to repre-nt the noi calculation for each module:
(/)jk jk k j k noi j P P j P T V i R L di dt ∈=
+×∑ (1)
where ()k noi V denotes the power supply noi at module k , P j denotes the path from VDD to node j , T k denotes the union of shortest paths and the cond shortest paths, R P jk de-notes the resistance of P jk , L P jk denotes the inductance of P jk and i j is the current flowing along path P j .
3.2 Decoupling Capacitance Budget Computation
In [1] and [2], the authors assume that the decap should fully supply the maximum current of the module, as shown in the white region in Fig. 3. Bad on this environment, the decap budget would be overly estimated. Actually, the VDD pin continually provides a current as the gray region in Fig. 3 when the chip is running. Therefore, the required decap size can be significantly reduced.
The required decap size can be easily obtained by the difference between the maxi-mum current (I max ) and the target current limit (I gen ) for each module. Assume the target current limit of module k is defined as ,k gen I k = 1, 2, …, M , and the maximum switching current of module k is max .k I Let C k be the required decap for circuit k and Q k is the amount of electric charge of the C k . Then Q k can be obtained by the following equation bad on the triangle model shown in Fig. 3.
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Fig. 3. Switching current consumption profile of module k .
1100 max ()()w w w w t t k k k gen t t Q I t dt I t dt =−∫∫ (2)
where t w 0 is the start time and t w 1 is the finish time when the target module is in opera-tional mode. The electric charge can be converted to the silicon area of the capacitance fabrication as follo
ws:
C k = Q k /V con (3) S decap = C decap /C ox (4) C ox = εox /t ox (5)
where V con is the noi constraint of the voltage, C decap is the decap budget and S decap is the silicon area of C decap . In order to verify our decap calculation model, we perform a simple experiment using SPICE and compare the required decap with [2]. In our experi-ment, the supply voltage is t to be 2.5V and the power supply noi limit is t to be 0.04V. If we adopt the [2] method to compute the require decap, the computation result is 112pF. The decap budget is 96pF if using Eq. (2) to compute. Our method could obtain the less required decap than [2].菠菜鸡蛋汤
4. SUPPLY NOISE AWARE FLOORPLANNING WITH MINIMAL DECAP INSERTION
4.1 O-tree Bad Power Supply Noi Aware Floorplanning
To obtain the better result of one noi-driven floorplan, a suitable and controllable floorplan reprentation is needed. We compare six floorplan reprentations, SP, B*-tree, O-tree, TCG, CBL, DBL. Finally, we choo O-tree to be our reprentation. The main reason is the adjacent relation co
uld be directly obtained. Therefore, the high current consumption modules could be easily placed at a distance.
O-tree is compod of a horizontal tree and a vertical tree, as shown in Figs. 4 (b) and (d). The horizontal (vertical) tree could u τ(α, β) to reprent the data structure, as shown in Fig. 4 (c). τ denotes the tree type and α denotes the paternity of the tree struc-ture, and β denotes the permutation of modules. If the module has horizontally (vertically) touch with another module, such as the modules H and L in Fig. 4, it could be easily ob-rved in the horizontal (vertical) reprentation. If we u another reprentation, the adjacent relation of each module must spend high cost to find. Therefore, we adopt the O-tree to be our floorplan reprentation.
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落雨天
(a) (c) (e)
Fig. 4. An O-tree example, (a) One floorplan result; (b) Vertical tree of A; (c) Vertical tree repre-
ntation; (d) Horizontal tree of A; (e) Horizontal tree reprentation.
Fig. 5. Using new delete method to delete the module J.
The original O-tree operation is shown in Fig. 5 (a). If module J is deleted, the original Delete operation would control remaining modules to make a LD-packing floor-plan. Two high-current modules (I and K) are placed at a tight location. Therefore, the current consumption of the chip would not be balance. In the special region, it would consume more power than other regions and must us more decap to solve power sup-ply noi. The similar situation is happened at the Inrt operation becau it only con-siders the area and the wire length in original operation. According to the previous de-scription, we know the original Otree operations could not control the neighbor block. Therefore, we need new transformation operations. The operations could avoid the high current consumption modules be placed at the continual location. Naturally, our decap inrtion approach could averagely plan the decap location according to the result of the floorplan. We propo two new transformation operations:
− Delete : The original operation delete the lected module only. The new operation would delete the lect module and top-right modules of the lect center together. − Inrt : The original operatio
n consider area factor only. The module would be inrted into the low noi location and the extensive area could be minimized.
Our Delete operation could be divided into veral steps. Firstly, we choo the de-lete module ν from the β location of the horizontal and vertical reprentation. Further, (b) (d)
