南 昌 工 程 学 院
2007 级毕业（设计）论文
信息工程学院 系（院） 电子信息工程 专业
中英文献翻译
题 目 基于超声波检测的倒车雷达设计（硬件设计）
学 生 姓 名 崔 凯
班素颜霜的作用 级小睡片刻武乡县公安局 2007电子信息工程 象龙
学 号 2007100153
指 导 教 师 曾 任 贤
日 期 2011 年 03 月 21 日
南 昌 工 程 学 院 教 务 处 订 制
AT89C2051 Microcontroller Instructions
1.1 Features
∙ Compatible with MCS-51 Products
∙ 2 Kbytes of Reprogrammable Flash Memory
Endurance: 1,000 Write/Era Cycles
钙片∙ 2.7 V to 6 V Operating Range
∙ Fully Static Operation: 0 Hz to 24 MHz
∙ Two-Level Program Memory Lock
∙ 128 x 8-Bit Internal RAM
∙ 15 Programmable I/O Lines
∙ Two 16-Bit Timer/Counters
∙ Six Interrupt Sources
∙ Programmable Serial UART Channel
∙ Direct LED Drive Outputs
∙ On-Chip Analog Comparator
∙ Low Power Idle and Power Down Modes
1.2 Description
The AT89C2051 is a low-voltage, high-performance CMOS 8-bit microcomputer with 2 Kbytes of Flash programmable and erasable read only memory (PEROM). The device is manufactured using Atmel’s high density nonvolatile memory technology and is compatible with the industry standard MCS-51 instruction t and pinout. By combining a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel AT89C2051 is a powerful m
icrocomputer which provides a highly flexible and cost effective solution to many embedded control applications.
The AT89C2051 provides the following standard features: 2 Kbytes of Flash, 128 bytes of RAM, 15 I/O lines, two 16-bit timer/counters, a five vector two-level interrupt architecture, a full duplex rial port, a precision analog comparator, on-chip oscillator and clock circuitry. In addition, the AT89C2051 is designed with static logic for operation down to zero frequency and supports two software lectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, rial port and interrupt system to continue functioning. The Power Down Mode saves the RAM contents but freezes the oscillator disabling all other chip functions until the next hardware ret.
1.3 Pin Configuration
1.4 Pin Description
VCC Supply voltage.
GND Ground.
Port 1
Port 1 is an 8-bit bidirectional I/O port. Port pins P1.2 to P1.7 provide internal pullups. P1.0 and P1.1 require external pullups. P1.0 and P1.1 also rve as the positive input (AIN0) and the negative input (AIN1), respectively, of the on-chip precision analog compa
rator. The Port 1 output buffers can sink 20 mA and can drive LED displays directly. When 1s are written to Port 1 pins, they can be ud as inputs. When pins P1.2 to P1.7 are ud as inputs and are externally pulled low, they will source current (IIL) becau of the internal pullups.
Port 1 also receives code data during Flash programming and program verification.
Port 3
Port 3 pins P3.0 to P3.5, P3.7 are ven bidirectional I/O pins with internal pullups. P3.6 is hard-wired as an input to the output of the on-chip comparator and is not accessible as a general purpo I/O pin. The Port 3 output buffers can sink 20 mA. When 1s are written to Port 3 pins they are pulled high by the internal pullups and can be ud as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) becau of the pullups.
Port Pin | Alternate Functions | 教师行为的转变
P3.0 | RXD (rial input port) |
P3.1 | TXD (rial output port) |
版籍P3.2 | INT0 (external interrupt 0)手抓饼要放油吗 |
P3.3 | INT1 (external interrupt 1) |
P3.4 | T0 (timer 0 external input) |
P3.5 | T1 (timer 1 external input) |
| |
Port 3 also rves the functions of various special features of the AT89C2051 as listed below:
1.5 Oscillator Characteristics
XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier which can be configured for u as an on-chip oscillator, as shown in Figure 1. Either a quartz crystal or ceramic resonator may be ud. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 2. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divideby-two flip-flop, but minimum and maximum voltage high and low time specifications must be obrved.
1.6 Special Function Registers
A map of the on-chip memory area called the Special Function Register (SFR) space is shown in the table below.
Note that not all of the address are occupied, and unoccupied address may not be implemented on the chip. Read access. to the address will in general return random data, and write access will have an indeterminate effect.
Ur software should not write 1s to the unlisted locations, since they may be ud in future products to invoke new fea tures. In that ca, the ret or inactive values of the new bits will always be 0.
1.7 Restrictions on Certain Instructions
The AT89C2051 and is an economical and cost-effective member of Atmel’s growing family of microcontrollers. It contains 2 Kbytes of flash program memory. It is fully compatible with the MCS-51 architecture, and can be programmed using the MCS-51 instruction t. However, there are a few considerations one must keep in mind when utilizing certain instructions to program this device.
