Cadence Encounter Tutorial
Cadence Encounter goes far beyond Silicon Enmble. It offers a single cockpit for the entire physical implementation flow. Although some tools are run as external binaries (e.g. Nanoroute), the ur never has to leave the GUI. In addition, the Common Timing Engine is integrated into Encounter, allowing for timing analysis every step of the way.
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This demo is bad on the IIT cell library. In addition, download the following files:
选题来源▪ The design configuration file: 焗油膏的正确用法
▪ The GDS mapping file: gds2_encounter.map
▪ The SDC constraints file: nrd_05.sdc
▪ The gate level netlist: nrd_05.v
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(Note that you will need to edit the path to the IIT cell library in the "f " file to match your local installation.) 捞汁怎么调
To prepare a design for Encounter, simply output a gate-level verilog netlist from the synthesis tool (e.g. Cadence PKS or Synopsys Design Compiler). In addition, for a timing driven flow also create a constraints file using the "write_sdc" command (in PKS or DC). Both the names of the netlist and constraint file, as well as all library files are summarized in "f". Using a conf file is the perfect way to organize the many parts that make up a design. And the bulk of the conf file will be constant for a particular cell library.
Floorplanning
Start Encounter with the Unix command
不相上下的意思encounter
The GUI will appear as in the following picture. To zoom in, draw a box with the right mou
button. To go back to full view, hit "f". (In this webpage, clicking on a screen shot will open the full image in a new window).
The first step is to import the design. Encounter us configuration files to neatly organize
the many pieces that make up a design. Do to "Design -> Design Import", hit "" and load in the file called "f". It should look like this:
Hit OK and the design as well as the library data is loaded. Next we need to create a floorplan. Do "Floorplan -> Specify Floorplan". Set the Core Utilization to 0.5 and the space between the core and the boundary to 30um on all sides. A utilization of 50% leaves enough room for buffer inrtion during optimization. Inside the 30um we will place supply rings.
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