Tufts University Cadence AMS-Designer Tutorial Written by Michael Trakimas
February 2007
Table of Contents
1.Introduction (3)
2.Initial Setup (3)
3.Ideal DAC Design Example (4)
单身party4.Simulation with AMS-Designer (7)
5.Additional Documentation (14)
1.Introduction
This tutorial is meant to give the reader enough information to begin using AMS-Designer in Cadence. The tutorial will go over tting up the AMS environment, and will go over the design of an ideal DAC. It will also give an overview of the interconnect modules, which are necessary to connect analog and di
gital blocks to each other. The tutorial is tailored for u by students at Tufts University, but should be applicable to Cadence installations at other institutions. More in-depth information can be found in the documentation supplied by Cadence, which is listed in the Additional Documentation ction of this tutorial.
AMS-Designer is a simulation environment which allows the simulation of mixed-signal designs. The simulator us Spectre and NC-Verilog to simulate the analog and digital parts respectively. Interconnect modules are ud to translate signals between analog and digital ports which are connected together. Another mixed-signal simulator available in Cadence is SpectreVerilog. AMS-Designer is recommended over SpectreVerilog
becau it can handle VerilogAMS code, and also us a better waveform viewer. SpectreVerilog us the same waveform viewer as Spectre, which is designed for displaying analog data. AMS-Designer us SimVision to plot the output waveforms. SimVision is able to plot analog and digital data much clearer than the Spectre waveform viewer.
It is necessary to note that AMS-Designer and the other mixed-signal simulators are still fairly new tools. More work must be done on them before they can be ud as easily and reliably as the simulators that are dedicated to either analog or digital simulation. For this reason, it is recommended that mixed-signal simulation is only ud when necessary. It is more appropriate to design parate blocks, which only include digital or analog parts. The blocks can be verified using the more established simulators such as Spectre and Verilog-XL. The individual blocks can then be connected together at the top-level, and the behavior of the whole circuit can be verified with AMS-Designer.
2.Initial Setup
Before using AMS-Designer, a file named ‘hdl.var’ should be created in the directory which you launch Cadence from. This file is not absolutely necessary, but it will suppress warnings and prevent some unwanted behavior. The following content should be included in your ‘hdl.var’ file.
softinclude $INSTALL_DIR/tools/inca/files/hdl.var
define ams
define NCVLOGOPTS -linedebug
define VIEW_MAP ($VIEW_MAP, .vs => shell)
define WORK //my_design_library_name//
$INSTALL_DIR is the directory where Cadence was installed. At Tufts University, the installation directory for the mixed-signal parts of Cadence is
‘/loc/packages/cadence/solaris/IUS54/’. The line ‘define WORK…’ is included to tell AMS-Designer which library to arch for files. This line should be omitted if the
‘hdl.var’ file will be ud for multiple designs in different libraries.
The following line should be added to your ‘cds.lib’ file.
SOFTINCLUDE $INSTALL_DIR/tools/inca/files/cds.lib
3.Ideal DAC Design Example
The following example will take you through the steps in order to design and simulate an ideal DAC using AMS designer. The example assumes that the reader is familiar with the Cadence design environment, as well as with modeling in verilog and verilogA.
To begin with, create a new library called ‘AMS_Tutorial.’ Next create a new verilogA cellview called ‘ideal_dac’ and copy the following code into it.
冷藏室温度// VerilogA for MprLibTest, ideal_dac, veriloga
`include "constants.h"
`include "discipline.h"
module ideal_dac(in, agnd, out);
不同英文
input [10:0] in;
input agnd ;
output out ;
electrical [10:0] in ;
electrical agnd ;
electrical out ;
parameter real logic_thresh = 2.5;
parameter real full_scale = 1.0 ;
parameter real tri = 1n from [0:inf);
parameter real tfall = 1n from [0:inf);
real code, delta ;
real pow2 [11:0] ;
integer i ;
analog begin
@(initial_step) begin
pow2[0] = 1.0 ;
for (i=1;i<=11;i=i+1) pow2[i] = 2.0 * pow2[i-1] ;
end
code = 0.0 ;旅程
羊肉怎么做// for (i=0;i<11;i=i+1) begin
generate j (10,0) begin
if (V(in[j]) < logic_thresh) delta = 0.0 ;
el delta = pow2[j] ;
code = code + delta ;
end
if (V(in[10]) > logic_thresh) code = code - pow2[11] ;
code = full_scale * code / pow2[10] ;
V(out) <+ V(agnd) + transition(code, 0, tri, tfall);
end
endmodule
After saving this file, make sure to create a symbol for the cellview. Next create a verilog cellview called ‘dac_driver’ and copy the following code into it.
module dac_driver (word_out);
output [10:0] word_out;
reg [10:0] word_out;
begin
initial
word_out = 12'h000;
#20480 $finish;
end
always #5 word_out = word_out + 1'b1;
endmodule
After saving this file, make sure to create a symbol for the cell view.周公解梦梦见洗头
The DAC driver will be ud to supply the ideal DAC with a linear quence of digital words. The ideal DAC reads in the digital data and outputs the corresponding analog values. This system contains both digital and analog signals, and therefore requires the u of a mixed-signal simulator. In order for the DAC driver, which is completely digital, to be able to talk to the analog ideal DAC, interconnect elements must be ud. Interconnect elements are ud to convert a digital (analog) signal into an analog (digital) signal, so that an analog port can be connected to a digital port. This is necessary to connect the digital output of the DAC driver to the analog input of the ideal DAC.
AMS-Designer can automatically inrt interconnect elements, but it is difficult to get this to work correctly, especially when you want to modify the elements for different analog-to-digital interface element will be given as well for completeness. There is also a bi-directional interface element, but the design and u of this is left to the reader. To create the analog-to-digital interface element, create a verilogams cellview called ‘a_d’. Be sure to u the VerilogAMS editor as shown in Fig. 1.
Copy the following code into the file, and create a symbol. The interconnect element given has been designed for a 5V supply voltage. The parameters can easily be modified to support the supply voltage ud in different designs.
// Enhanced Electrical to Logic Connect Module
//
// Version 1a, 1 June 04
//
// Olaf Zinke
//
// Downloaded from The Designer's Guide (www.designers-guide).
这货不是统治战场// Post any questions on www.designers-guide/Forum.
// Taken from "The Designer's Guide to Verilog-AMS" by Kundert & Zinke.
// Chapter 4, Listing 17.
`timescale 1ns / 1ps
`include "disciplines.vams"
connectmodule a_d (D, A);
parameter real vh = 4; // minimum voltage of a logic 1 (V)
parameter real vl = 1; // maximum voltage of a logic 0 (V)
parameter real c = 20f; // input capacitance (F)
parameter real dt = 1m; // time in x region before x is produced (s)
parameter real dv = 0.5; // voltage between threshold and x region (V)
input A;
output D;
electrical A;
reg D;
logic D;
parameter real vlx = vl + dv;
parameter real vhx = vh - dv;
reg inXregion;
initial inXregion = 0;
always @(above(V(A) - vh)) begin
D = 1'b1;
inXregion = 0;
end
always @(above(vl - V(A))) begin
D = 1'b0;
inXregion = 0;气球是球体吗
