DSM NO:G-03-MIXED_MODE/RFCMOS18-1.8V/3.3V-1P6M-MMC-TLR
Ver:2.9 Pha:1 Approved Date:06/05/2006
* BEGIN *
0.18 um Mixed-Mode and RFCMOS 1.8 V/3.3 V
1P6M Metal Metal Capacitor Process Topological
Layout Rule
(Ver. 2.9_P. 1)
Single-Poly 6-Metal (1P6M), Dual-Voltage (1.8 V/3.3 V)
P-Sub, Twin-Well Mixed-Mode and RFCMOS Process
1. Contents Page
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1.Contents1
2.Revision History3
3.Mask Layer Definitions15
4.Layout Rules16
4.1DIFFUSION16
4.2N_WELL18
4.3T_WELL19
4.4VTPL20
4.5VTPHL21
4.6P_WELL22
4.7VTNL23
4.8VTNI24
4.9VTNHL25
4.10VTN26
4.11P-26
4.12N-26
4.13TG27
4.14POLY128
4.15HR30
4.16N+32
4.17P+33
4.18SAB and Non-Salicided resistors34
4.19CONTACT36
4.20METAL137
4.21MVIA138
4.22METAL239
4.23MVIA240
4.24METAL341
交友的典故4.25MVIA342
4.26METAL443
4.27MVIA444
4.28METAL545
4.29METAL_CAP metal46
4.30MVIA549
4.31METAL6 and Inductor (20KA option)50
4.32PAD_WINDOW and Scribe Line53
4.33PESD53
5.Die Seal Ring Rules54
6.Metal Stress Relief Rules56
6.1Metal Slot Rules56
6.2Die Corner Rules57
Rules58开机自启动程序关闭方法
7.Antenna
8.Electromigration Rules59
8.1 DC rules59
8.2 AC rules60
9.FUSE Rules Refer Spec No.G-03F-GENERATION15_ABOVE-TLR/FUSE
10.ESD Rules Refer Spec No.G-03E-GENERATION18-TLR/ESD
11.Latch-up Rules Refer Spec No.G-03L-GENERATION18TLR/LATCH_UP
12.Bonding PAD Rules Refer Spec No.G-03P-GENERATION15_ABOVE-TLR/PAD
13.LOGO Rules61
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杭州建人高复学校
2. Revision History:
Ver.Pha Approved
Date Author /
船越义珍Revisor
From To Remark
(Purpo)
1.202/06/2001Diana
Chang --
4.6 P_WELL Layer
The digitized area of this layer is the same as
N_WELL layer, and the digitized definition is
clear.
4.3 T_WELL Layer (No. P90)
3C. Minimum N_WELL overlap T_WELL
1.5
(*) T_WELL have to be put inside the
N_WELL
Add PESD layer
4.6 P_WELL Layer
The digitized area of this layer is the same as
N_WELL layer, and the digitized definition is
Dark.
4.3 T_WELL Layer (No. P90)
3C. Minimum N_WELL boundary to T_WELL
1.5
(*) T_WELL must be surrounded by N_WELL.
The final N_WELL digitized region is generated
per SPEC. NO.:
G-06-MIXEDMODE/RFCMOS18-1.8V/3.3V-1P6
M-MMC-MASKTOOL.
2.1105/10/2002Jiann Liu 4.15 HR Layer
15D. Minimum SAB width for HR Poly resistor
(Define HR Poly resistor length) 1.5um
15F. Minimum HR to unrelated Poly spacing
5.0um
15O. Mimimum P+ implant spacing to
unrelated poly resistor 1.0um 4.15 HR Layer
15N. P+ implant overlap SAB 0.2
15D. Minimum SAB width for HR Poly resistor
(Define HR Poly resistor length) 1.0um
15F. Minimum HR to unrelated Poly spacing
2.0um
15O. Mimimum P+ implant spacing to unrelated
poly resistor 0.4um
15P. Minimum p+ implant layer overlap HR poly
0.3um
2A.b. N_WELL width for resistor
< N_WELL width for resistor
4.2.1
N_WELL Resistor Layer is for DIFFUSION dummy pattern non-creation on resistor.
N_WELL Resistor Layer can be optionally ud for sizing to eliminate sheet resistance discrepancy due to N_WELL effect.
4.4.C VTNL
4.5C VTNL
4.7F.Minimum VTNL extension over Poly of related device.
4.7G.Minimum VTNL to unrelated Poly spacing.
4.8F.Minimum VTNI extension over Poly of related device.
4.8G.Minimum VTNI to unrelated Poly spacing.2A.b. N_WELL resistor
< N_WELL resistor
4.2.1
N_WELL resistor layer is a drawn layer. It is ud to block the dummy DIFFUSION pattern during the mask data preparation.
4.4C VTPL
4.5C VTPHL
古城阆中4.7F.Minimum VTNL overlap Poly of related device
4.7G.Minimum VTNL to unrelated Poly spacing(in DIFFUSION region)
4.8F.Minimum VTNI overlap Poly of related device
4.8G.Minimum VTNI to unrelated Poly spacing(in DIFFUSION region)
4.9C. VTNL
4.9F.Minimum VTNHL extension over Poly of related device.
4.9G.Minimum VTNHL to unrelated Poly spacing.
4.13E.Minimum TG extension over poly of
3.3V device.
4.13F.Minimum TG to unrelated poly device.4.9C. VTNHL
4.9F.Minimum VTNHL overlap Poly of related device
4.9G.Minimum VTNHL to unrelated Poly spacing(in DIFFUSION region)
4.13E.Minimum TG overlap poly of 3.3V device.
4.13F.Minimum TG to unrelated poly device(in DIFFUSION region).
一人比划一人猜100个
Ver.Pha Approved Date Author / Revisor From To
Remark (Purpo)
2.1
1
05/10/2002
Jiann Liu
14L.Maximum Poly length on DIFFUSION if 14D.b-2 < 0.54 um 0.74 14M.Maximum Poly Length on DIFFUSION if 14H < 0.49 um 2.04.16 N+ Implant Layer (No. P98) :16E.Minimum N+ implant (inside N_WELL) to P+ DIFFUSION (inside P_WELL) spacing.16N.Maximum N+ DIFFUSION to the nearest P+ pick-up spacing (inside P_WELL) 20um 4.17P+ Implant Layer (No. P97) :
17E.Minimum P+ implant (inside P_WELL) to N+ DIFFUSION (inside N_WELL) spacing.17N.Maximum P+ DIFFUSION to the
nearest N+ pick-up spacing (inside N_WELL)
20um
上好课
Align to Logic TLR 2.1 15 N. P+ implant overlap SAB 0.2um 15O. P+ implant spacing to unrelated poly resistor 1.0um This rule also apply to T_WELL N+ implant.Delete (I/O, RAM, ROM, capacitor and diode are excepted) This rule also apply to T_WELL P+ implant Delete.(I/O, RAM, ROM, capacitor and diode are excepted)
19H.Put the CONTACTs in the DIFFUSION region as many as possible to avoid current drop by DIFFUSION resistance.
19I. CONTACT on Poly inside of DIFFUSION is not allowed.
* This is the revision to correct many typing
errors. The
major addings are
HR resistor
p+ overlap SAB rules
and p+/n+
implant notes for T_WELL.
Typing errors Added 20G. Minimum metal 1 coverage for every millimeter square area is 25 %. Note : It is strongly recommeded that metal coverage is even distributed in the whole chip; the more uniform, the better.
22G. Minimum metal 2 coverage for every millimeter square area is 25 %. Note : It is strongly recommeded that metal coverage is even distributed in the whole chip; the more uniform, the better.
24G. Minimum metal 3 coverage for every millimeter square area is 25 %.
badguyNote : It is strongly recommeded that metal coverage is even distributed in the whole chip; the more uniform, the better.
26G. Minimum metal 4 coverage for every millimeter square area is 25 %.
Note : It is strongly recommeded that metal coverage is even distributed in the whole chip; the more uniform, the better.
28G. Minimum metal 5 coverage for every millimeter square area is 25 %.
Note : It is strongly recommeded that metal coverage is even distributed in the whole chip; the more uniform, the better.
31G. Minimum metal 6 coverage for every millimeter square area is 25 %.
Note : It is strongly recommeded that metal coverage is even distributed in the whole chip; the more uniform, the better.
Align to 0.18um Logic TLR version 2.3
Align to 0.18um Logic TLR version 2.3
