Engineer-to-Engineer Note
EE-315
a
Technical notes on using Analog Devices DSPs, processors and development tools
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Changing the PHY in the Ethernet Driver for Blackfin® Processors
Contributed by Jiang Wu
观察力游戏Rev 1 – June 21, 2007
Copyright 2007, Analog Devices, Inc. All rights rerved. Analog Devices assumes no responsibility for customer product design or the u or application of customers’ products or for any infringements
of patents or rights of others which may result from Analog Devices assistance. All trademarks and logos are property Introduction
This EE-Note describes how to achieve networking functionality with ADSP-BF536/ADSP-BF537 Blackfin® processors together with MII-compatible Ethernet Physical Layer Transceivers (PHYs) other than the SMSC LAN83C185, which is populated on the ADSP-BF537 EZ-KIT Lite® evaluation system. The procedure is bad on the VisualDSP++® 4.5 development tool suite and its Ethernet MAC driver for the ADSP-BF537 processor. The work was verified on an SMSC LAN8187 and on a National Semiconductor DP83848.
Overview
ADSP-BF536/ADSP-BF537 Blackfin processors include a built-in Ethernet MAC controller, providing an IEEE 802.3-2002-compliant MII interface for easy connection to any MII-compatible PHY [1]. In addition, the VisualDSP++ 4.5 development tools are shipped with a driver for the MAC controller, a TCP/IP stack (LwIP ), and a project template for TCP/IP applications [2]. This allows you to start network-capable applications right away by using the standard BSD socket API. This network solution is illustrated in Figure 1.
The MAC controller driver provided by the
VisualDSP++ 4.5 tools is designed primarily for the SMSC LAN83C185 PHY device populated on the ADSP-BF537 EZ-KIT Lite evaluation board [3]. If you choo to u this development
system, you can code network applications without having to consider any hardware details [4]. However, if you u other PHYs, you must modify the MAC driver, becau the MAC driver us unique vendor-specific features in addition to MII standard PHY features.
Figure 1. Overview of ADSP-BF537 bad network applications
The source code of the MAC driver consists of three files.
The project file (ADI_ETHER_BF537.dpj ) and the C source file (ADI_ETHER_BF537.c) are located in the following directory:
<install_path>\Blackfin\lib\src\drivers \ethernet\ADI_ETHER_BF537\
The ADI_ETHER_BF537.h file is located in:
<install_path>\Blackfin\include\drivers \ethernet\
The files are copied automatically when the VisualDSP++ 4.5 tools are installed. Opening the project file and building it with the VisualDSP++ 4.5 development tools generates a library file named ADI_ETHER_BF537.dlb, which can then be linked to the network application[5].
The MAC driver is the connecting bridge between the physical MAC controller/PHY and the software TCP/IP stack (LwIP). On one side, it us two dedicated DMA channels (DMA1 and DMA2) for the network data exchange between the MAC controller and the system memory. On the other side, it communicates with the TCP/IP stack through a message box mechanism.
The MAC controller talks to the PHY via the MII interface, which includes two parts, the network data exchange (signals RxD[3:0], Rx_DV, Rx_CLK, and Rx_ER for receiving; and TxD[3:0], Tx_EN, Tx_CLK, and Tx_ER for transmitting), and the management data exchange (signals MDC and MDIO). The driver controls the MAC controller by writing/reading its memory-mapped registers (MMRs). It also manages the PHY by commanding the MAC controller to write/read the 32 PHY registers via the MII management data exchange channel.
The first two of the 32 PHY registers, the Control Register (register 0) and the Status Register (register 1), are mandatory, according to the MII specification, while the following 13 registers (regist
ers 2-15) are the optional extended register t. The remaining registers (registers 16-31) are vendor-specific. In the following ction, the required modifications to the MAC driver source code to accommodate different PHYs will be described. Modifying the MAC Driver Code
To enable the MAC driver for the ADSP-
BF536/ADSP-BF537 processor to work with different PHYs, you must first modify the
ADI_ETHER_BF537.c source code file as described in the following ctions.
Required changes to the source code
are explained in RED font in the code
shown in the following steps.
To make it easy to find the change locations, a modified version of ADI_ETHER_BF537.c is included in the .ZIP file associated with this EE-
策划案怎么做Note[6], in which all the change locations are marked with a comment /*PHY_CHANGE_LOCATION*/.
static u32 adi_pdd_Open()
This function determines all the default ttings
of the PHY, such as PHY address, full/half
duplex mode, speed, and auto-negotiation. They
can be t here or in the application code by
calling the device control function
adi_dev_Control() with the corresponding COMMAND. The ttings must be done only after
adi_dev_Open() and before adi_dev_Control(…, ADI_ETHER_CMD_START,
…).
dev->PhyAddr = 0x01; // 0x01 1.1 EZ kit and BUB, Changed to reflect the new PHY’s address. The PHY’s address is ud by the MAC’s MII management interface
to identify each PHY, since MII is able to manage up to 32 PHYs with the
same interface. It is usually determined by the strap option pins of the
PHYs. The values of the pins are sampled during PHY ret and are ud
to strap the device into specific address.
dev->CLKIN = 25; //Ezkit, Changed to reflect the new application system’s oscillator/crystal clock in unit of MHz. It will later be ud for
tting up the MDC frequency. According to the MII standard, the minimum
high and low times for the MDC signal shall be 160 ns each, and the
minimum period for MDC shall be 400 ns. The driver us this CLKIN value环保宣传标语
to t up a MDC clock of 2.5MHz.
dev->FullDuplex=fal; //Changed to reflect the new PHY’s Full Duplex capability
dev->Negotiate = true; //Changed to reflect the new PHY’s AUTONEGOTIATION
capability. If the PHY doesn’t support it, the driver code must be
changed to t the PHY’s capability correctly, which includes dev-
>FullDuplex and dev->Port10. A TRUE value of dev->Port10 means 10MBa,
otherwi it is 100MBa.
static SetPhy()
This function is called when the application issues the ADI_ETHER_CMD_START command to the MAC driver by calling adi_dev_Control (…, ADI_ETHER_CMD_START, …). It initializes the PHY using the default parameters t in the adi_pdd_Open()function.
Set software ret
// issue a ret
RawWrPHYReg(dev->PhyAddr, PHYREG_MODECTL, 0x8000);
// wait half a cond
period = 30000000; // assume 600 MHZ, This provides a pure delay to allow the PHY to complete a
software RESET. It needs to be changed to reflect the new
PHY’s requirements and the application system’s clock. The MII standard
requires the RESET process be completed within 0.5 conds from the
issuing of a software ret.
ndtime = clock()+period;
while (clock()<ndtime);
Configure ttling time
belgrade
WrPHYReg(dev->PhyAddr, PHYREG_MODECTL, phydat);
period = 100000000; // assume 600 MHZ, Similar to step 2, it provides a pure delay to allow the new control ttings to take effect, changed to reflect the
new PHY’s requirements
ndtime = clock()+period;
while (clock()<ndtime);
Check PHY ID
if ((RdPHYReg(dev->PhyAddr, PHYREG_PHYID1) == 0x7) && ((RdPHYReg(dev->PhyAddr, PHYREG_PHYID2)&0xfff0 ) == 0xC0A0)) { // check PHYID, It checks the ID
甜的反义词
of the PHY to ensure the connected PHY is LAN83C185(the PHY on the ADSP-
BF537 EZ-Kit Lite evaluation platform) by reading the 2 PHYID registers
of the PHY. It needs to be changed to reflect the new PHY’s ID, which
can be found in the datasheet of the PHY.
Enable PHY interrupt
WrPHYReg(dev->PhyAddr, 30, 0x0ff); // enable interrupt, It enables the interrupt of the PHY by writing a vendor-specific register (#30). It needs to be
changed to new PHY’s counterpart. The enabling of the PHY interrupt also
requires the physical connection of the PHY’s interrupt pin to the ADSP-
BF537 processor’s PHY_INT pin. If the developer decides not to u the
interrupt, this instruction can be commented out.
static
ADI_INT_HANDLER(EtherInterruptHandler) This function is the interrupt rvice routine (ISR) for the MAC controller interrupt. The interrupt may come from the PHY, the MAC management counter, the Rx frame status, the Tx frame status, and so on[1]. However, the current version of the driver process only the PHY interrupt and the MAC management counter interrupt. The PHY interrupt is indicated by the asrtion of the INT pin of the PHY and is nd by the ADSP-BF537 processor at the PHY_INT pin if the two pins are connected. If you choo to u the PHY interrupt, you must provide your own rvice code in the if(systat&0x01){…} block in this function. At a minimum, the rvice code should read and clear the PHY interrupt status bits. Note that different PHYs usually have different interrupt structure and capability. The current MAC driver takes auto-negotiation mode by default, so it ts the full/half duplex mode and PAUSE capability according to its link partners’ ability.
if (systat&0x01) {
//PHY_INT
full=0;
int
opmode;
u32
reg3,reg2,reg,phydat;
u16
reg2 = RdPHYReg(dev->PhyAddr,2); // read PHY id 1
reg3 = RdPHYReg(dev->PhyAddr,3); // read PHY id 2
if ((reg2 == 0x07) && ((reg3>>4) == 0xc0a)) { // Similar to step 3, check the ID of the PHY to ensure the connected PHY is LAN83C185 (the PHY on the
ADSP-BF537 EZ-Kit Lite evaluation platform). Change to reflect the new
PHY’s ID.
// SMSC LAN83C185
reg = RdPHYReg(dev->PhyAddr,31); // read special status, this is to read the PHY’s speed indication to determine whether full or half duplex is
being ud. Change this instruction and the next one to reflect the new
PHY.
full = (reg&0x10);
if (full) {内扣发型图片
// does remote link support flow control
phydat = RdPHYReg(dev->PhyAddr,PHYREG_ANLPAR);
dev->FlowControl = (phydat &0x0400); // get the PAUSE capability of
the link partner and t the PAUSE option of the MAC controller
accordingly in the following instruction
if (dev->FlowControl) {
// we enable flow control
*pEMAC_FLC = FLCE; /* flow control enabled */
// advertize flow control supported
}
}
}
疫情学校
opmode = *pEMAC_OPMODE;
if (full) {
童年主要内容
opmode |= 0x04000000;
} el {
opmode &= 0xfbffffff;
}
*pEMAC_OPMODE = opmode; // Set the Full/half duplex mode of the MAC controller according to the PHY’s current mode
systat = RdPHYReg(dev->PhyAddr,29); // read interrupt sources, read the source of the current PHY interrupt and clear it. Change to reflect the new
PHY. The interrupt event and the status (systat) are to be pasd to the
interrupt callback function. However, the callback of the current
version of the driver does not do any further processing.
event = ADI_ETHER_EVENT_INTERRUPT_PHY;
result = ADI_INT_RESULT_PROCESSED;
}
