>>>>>>### Read design file #
//
read –format verilog[db、vhdl] file //dcsh的工作模式
read_db file.db //TCL工作模式读取 DB格式
read_verilog file.v //TCL工作模式读取verilog格式
read_vhdl file.vhd //TCL工作模式读取VHDL格式
//设定时钟
create_clock -name "clock" -period 20 -waveform { 0.000 10.000 } { clk }
//输出文件
write -f verilog -out output/count.v //输出网表
write -f ddc -out output/count.ddc//综合数据文件
write_sdf mapped/count.sdf //标准延时文件
//综合
compile -map_effort medium -incremental_mapping
tip6设置设计环境Define the Design Environment
1. Defining the Operating Conditions设置操作环境
查看有哪些操作环境
dc_shell> read_file my_lib.db
dc_shell> report_lib my_lib
指定操作环境
dc_shell> t_operating_conditions WCCOM -lib my_lib
2.设置线负载模型
t_wire_load_mode Top/Enclod/Segmented
t_wire_load_model "10x10"
3. Modeling the System Interface设置系统接口
The t_drive and t_input_transition Commands：
dc_shell> current_design top_level_design
dc_shell> t_drive 1.5 {I1 I2}
dc_shell> current_design sub_design2
dc_shell> t_driving_cell -lib_cell IV {I3}
dc_shell> t_driving_cell -lib_cell AN2 -pin Z -from_pin B {I4}
讲故事英语Defining Loads on Input and Output Ports
Defining Fanout Loads on Output Ports
4. Setting Logic Constraints on Ports
t_equal port1 port2
t_opposite
t_logic_dc
t_logic_one
t_logic_zero
t_unconnected
tip7设定 设计约束
When Design Compiler optimizes your design, it us two types of constraints:邓旋
Design rule constraints
Optimization constraints
1. Maximum Transition Time
dc_shell> t_max_transition 5 [current design]
2. Maximum Fanout
You can t a maximum fanout constraint on every driving pin and input port as follows:
dc_shell> t_max_fanout 8 [get_designs ADDER]
计算Fanout值：
Maximum Fanout>=Total Fanout Load
注意：取出某些约束用：
dc_shell> remove_attribute [get_designs adder] max_transition
dc_shell> remove_attribute [get_ports port_name] max_fanout
世界上最小的坦克dc_shell> remove_attribute [get_designs design_name]max_fanout
dc_shell> remove_attribute port_name fanout_load
3. The t_fanout_load command ts the expected fanout load value for listed output ports.
To find the fanout load on the input pin of library cell AND2 in library libA, enter
dc_shell> get_attribute "libA/AND2/i" fanout_load
展望未来的成语To find the default fanout load t on technology library libA, enter
dc_shell> get_attribute libA default_fanout_load
郑真4. Maximum Capacitance
Maximum capacitance is a design rule constraint. It is t as a pin-level attribute that defines
the maximum total capacitive load that an output pin can drive. That is, the pin cannot connect to a net that has a total capacitance greater than or equal to the maximum capacitance defined at the pin.
dc_shell> t_max_capacitance 3 [get_designs adder]
5. Minimum Capacitance康乃馨代表什么
The min_capacitance design rule specifies the minimum load a cell can drive.
设计规则的优先权
1. Minimum capacitance
2. Maximum transition
3. Maximum fanout
4. Maximum capacitance
5. Cell degradation
tip8设定优化约束Optimization Constraints
Timing Constraints
对于同步pashs
