专利名称：MEMORY ARRAY HAVING A SEGMENTED BIT LINE ARCHITECTURE
opggg发明人：FISCH, DAVID,BRON, MICHEL
钟表手工
申请号：US2007015717
斗牛比赛
申请日：20070710
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公开号：WO2008008329A3
公开日：
20081002浅秋
专利内容由知识产权出版社提供
二面角的求法摘要：An integrated memory circuit device having a memory cell array (102) including a plurality of bit lines (e.g., 32a, 32b) and a plurality of bit line gments (e.g., 32a1, 32b1) wherein each bit line gment is coupled to an associated bit line (32a, 32b). The memory cell array (102) further includes a plurality of memory cells (12), wherein each memory cell (12) includes a transistor (14) having a first region, a cond region, a body region, and a gate coupled to an associated word line (28) via an associated word line gment. A first group of memory cells (12) is coupled to the first bit line (32a) via the first bit line gment (32a1) and a cond group of memory cells (12) is coupled to the cond bit line (32b) via the cond bit line gment (32b1). A plurality of isolation circuits (104), dispod between each bit line gment (32a1, 32b1) and its associated bit line (32a, 32b), responsively connect the associated bit line gment to or disconnect the associated bit line gment (32a1, 32b1) from the associated bit line (32a, 32b).
申请人：INNOVATIVE SILICON S.A.,FISCH, DAVID,BRON, MICHEL
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