DS04–21314–1E
Copyright
© 1994 by FUJITSU LIMIED
MB1519 ASSP
DUAL SERIAL INPUT PLL FREQUENCY SYNTHESIZER
工商管理实习报告
NOTE:
Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions as detailed in the operational ctions of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
PIN ASSIGNMENT
This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. However,it is advid that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit.烩松肉
TOP DUAL SERIAL INPUT PLL FREQUENCY SYNTHESIZER
WITH 600MHz PRESCALER
The Fujitsu MB1519 is a 600MHz dual rial input PLL (Pha Locked) frequency synthesizer designed for cellular telephone and cordless telephone applications.
The MB1519 has two PLL circuits on a single chip: one for transmit and the other for reception.Separate power supply pins are provided for the transmit and reception PLL circuits. Transmit PLL contains a low nsitivity charge pump for ea of modulation and reception PLL contains a high nsitivity charge pump for faster lock up time.
600 MHz dual modulus prescalers are on chip and enables a pul swallow function.It operates supply voltage of 3.0V typ. and dissipates 11mA typ. of current realized through the u of Fujitsu’s unique U-ESBIC Bi-CMOS technology.
•High operating frequency: fin = 600MHz
•Low power supply voltage: V CC = 2.7 to 5.5V •Low power supply current: I CC = 11mA typ, @3V.•Wide operating temperature: T A = –40 to 85°C •Two charge pumps
Low nsitivity charge pump for transmit High nsitivity charge pump for reception •
Plastic 20-pin dual in line package (Suffix: -P)Plastic 20-pin flat package (Suffix: -PF)
123456GND OSC OUT
fin 1OSC IN
V CC1
fr Data LE fin 2V CC2fp 78910
LD 1V P1D O1BS 1
LD 2V P2D O2BS 2
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VIEW
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奇数和偶数是什么
Data
MB1519
MB1519 BLOCK DESCRIPTIONS
TRANSMIT/RECEPTION BLOCK
•20-bit latch
•Programmable divider consisting of:
Binary 7-bit swallow counter (Divide ratio: 0 to 127)
Binary 11-bit programmable counter (Divide ratio: 16 to 2047)
傍生
•Pha detector with pha polarity change function
•600MHz dual modulus prescaler (Divide ratio: 64/65)
•Charge pump
COMMON BLOCK
•23-bit shift register
•Programmable divider consisting of:
Reference counter (Divide ratio: 512, 1024)
(Divide frequency = 25kHz, 12.5kHz (Crystal oscillator frequency = 12.8MHz)
•Crystal oscillator
•fp monitor output lector
女兵谣歌词•Latch lector
•Schmitt circuits
•Analog switches
MB1519
PIN DESCRIPTIONS
MB1519 PIN DESCRIPTIONS (Continued)
FUNCTIONAL DESCRIPTIONS
The divide ratio can be calculated using the following equation:
f VCO = {(M x N) + A} x f OSC÷R (A < N)
f VCO:Output frequency of external voltage controlled ocillator (VCO)
M:Pret divide ratio of dual modulus prescaler (64)
N:Pret divide ratio of binary 11-bit programmable counter (16 to 2047)
凤城中学A:Pret divide ratio of binary 7-bit swallow counter (0≤ A ≤127)
f OSC:Reference oscillator frequency
R:Pret divide ratio of reference counter (512 or 1024)
MB1519
简历求职意向FUNCTIONAL DESCRIPTIONS
SERIAL DATA INPUT
Serial data is input using three pins, Data pin, Clock pin, and LE pin. Programmable divider of transmit ction and programmable divider of recep-tion ction are controlled individually.
Serial data of binary data is input into Data pin.
On rising edge of clock shifts one bit of rial data into the shift register. When load enable signal is high, the data stored in the shift register is transferred to either the latch of transmit ction or the latch of reception ction depending upon the control bit data tting.
Control data Destination of rial data
H Latch of transmit ction
L Latch of reception ction
SHIFT REGISTER CONFIGURATION
Control bit
N1 to N11: Divide ratio of the programmable counter tting bit (16 to 2047)
A1 to A7: Divide ratio of the swallow counter tting bit (0 to 127)
FC: Pha control bit of the pha detector
DMY: Dummy bit (ts to low)
FP: Output of the programmable divider control bit (fp1 or fp2)
REF: Divide ratio of the reference counter tting bit (512 to 1024)
CNT: Control bit
SERIAL DATA INPUT TIMING
On rising edge of the clock shifts one bit of the data into the shift register.
