CMOS IC LC866448B/44B/40B/36B/32B/28B/24B/20B/16B/12B/08B炒菜心
8-Bit Single Chip Microcontroller
Preliminary
Overview
The LC866448B/44B/40B/36B/32B/28B/24B/20B/16B/12B/08B microcontrollers are 8-bit single chip microcontrollers with the following on-chip functional blocks:
- CPU : Operable at a minimum bus cycle time of 0.5µs (microcond)
- On-chip ROM Maximum Capacity : 48K bytes
- On-chip RAM Capacity : 1152/768/640/512 bytes
(LC866448B/44B/40B/36B/32B/28B/24B/20B/16B/12B/08B)
- 16-bit timer /counter (or two 8-bit timers)
- 16-bit timer /PWM (or two 8-bit timers)exerci可数吗
- 8-channel × 8-bit AD converter
- Two 8-bit synchronous rial-interface circuits (1-channel × 16bit, 1-channel × 8bit)
- 14-source 10-vectored interrupt system
All of the above functions are fabricated on a single chip.
Features
(1) Read-Only Memory (ROM) : LC866448B 49152 × 8 bits : LC866444B 45056 × 8 bits : LC866440B 40960 × 8 bits : LC866436B 36864 × 8 bits : LC866432B 32768 × 8 bits : LC866428B 28672 × 8 bits : LC866424B 24576 × 8 bits : LC866420B 20480 × 8 bits : LC866416B 16384 × 8 bits : LC866412B 12288 × 8 bits : LC866408B 8192 × 8 bits (2) Random Access Memory (RAM) : LC866448B/44B/40B/36B 1152 × 8 bits : LC866432B/28B/24B 768 × 8 bits : LC866420B/16B 640 × 8 bits : LC866412B/08B 512 × 8 bits (3) Bus Cycle Time/Instruction Cycle Time
The LC866448B/44B/40B/36B/32B/28B/24B/20B/16B/12B/08B are constructed to read ROM twice
within one instruction cycle. It has 1.7 times more performance capability within the same instruction cycle compared to our 4-bit microcomputers (LC66000 ries).婴儿吃完奶打嗝
Bus cycle time indicates the speed to read ROM.
Bus cycle time
Cycle time
Clock divider
System clock oscillation Oscillation Frequency
Voltage 0.5µs 1µs 1/1 Ceramic resonator oscillation 6MHz 4.5V to 6.0V 2µs 4µs 1/1 Ceramic resonator oscillation 3MHz 2.5V to 6.0V 7.5µs 15µs 1/1 RC resonator oscillation 800kHz 2.5V to 6.0V 183µs 366µs
1/2
五味子功效
Crystal oscillation
32.768kHz
2.5V to 6.0V
(4) Ports
- Input/output ports : 1 port (8 terminals : port 1) Input/output programmable in a bit - 15V withstand Input/Output ports : 2 ports (12 terminals) Input/output port programmable in nibble unit : 1 port (8 terminals : port 0)
(When the N-channel open drain output is lected, the data in a bit can be inputted.) Input/output port programmable in a bit : 1 port (4 terminals : port 3) - Input port : 2 ports (14 terminals : port 7,8) - VFD output port : 38 terminals Large current output for digit : 16 terminals Pull-down resistor option available - Other function Input/output port : 1 port (6 terminals : port E) Input port : 2 ports (16 terminals : port C,D) (5) VFD automatic dislay controller
-Segment/digit output pattern programmable Any gment/digit combination available VFD parallel-drive available - 16-step dimmer function available (6) AD converter
- 8-channel × 8-bit AD converter (7) Serial-interface
- 1 channel × 16-bit rial-interface circuits - 1 channel × 8-bit rial-interface circuits - LSB first / MSB first function available
- Internal 8-bit baud-rate generator in common with two rial-interface circuits
(8) Timer
- Timer 0
16-bit timer/counter
子午流注口诀2-bit prescaler + 8-bit programmable prescaler
Mode 0 : Two 8-bit timers with programmable prescaler
Mode 1 : 8-bit timer with programmable prescaler + 8-bit counter
Mode 2 : 16-bit timer with programmable prescaler
Mode 3 : 16-bit counter
The resolution of Timer is tCYC. (tCYC: cycle time)
- Timer 1
16-bit timer/PWM
Mode 0 : Two 8-bit timers
Mode 1 : 8-bit timer + 8-bit PWM
Mode 2 : 16-bit timer
Mode 3 : Variable-bit PWM (9-16 bits)
In Mode 0 and Mode 1,the resolution of Timer and PWM is tCYC.蒜泥生菜的做法
In Mode 2 and Mode 3,the resolution of Timer and PWM lectable: tCYC or 1/2 tCYC by program - Ba timer
Every 500ms overflow system for a clock application (using 32.768kHz crystal oscillation for Ba timer clock)
Every 976µs, 3.9ms, 15.6ms, 62.5ms overflow system (using 32.768kHz crystal oscillation for Ba t
imer clock)
The Ba timer clock lectable; 32.768kHz crystal oscillation, System clock, and programmable prescaler output of Timer 0
(9) Buzzer output
- The Buzzer sound frequency lectable; 4KHz, 2KHz (using 32.768kHz crystal oscillation for Ba
timer clock)
(10) Remote-control receiver circuit (Shares with the P73/INT3/T0IN terminal)
- Noi Rejection function (the time constant of noize rejection filter: 1tCYC/16tCYC/64tCYC)
(tCYC: instruction cycle time)
- Switch Polarity function
(11) Watchdog timer
- The watchdog timer is taken on RC outside
- Watchdog timer operation lectable: interrupt system, system ret
(12) Interrupt system
- 14-source 10-vectored interrupts :
1. External interrupt INT0 (include watchdog timer)
2. External interrupt INT1
3. External interrupt INT2, Timer/counter T0L (Lower 8-bit)
4. External interrupt INT3, Ba timer
5. Timer/counter T0H (Upper 8-bit)
6. Timer T1L, Timer T1H
7. Serial-interface SIO0
8. Serial-interface SIO1
9. AD converter
10. VFD automatic display controller, Port 0
- Built-in Interrupt Priority control register
Microcontroller allows 3 levels of interrupt; low level, high level, and highest level of multiplex interrupt. It can specify a low level or a high level interrupt priority from INT2/T0L through port 0
(i.e. the above interrupt number from three through ten). It can also specify a low level or the highest level interrupt
priority to INT0 and INT1.
(13) Real-time rvice operation
The Real-Time Service (RTS) functions the 4-byte data-transfer between the Special Function Registers at acknowledging the interrupt request.
The RTS starts within 1 instruction cycle-time and completes within 5 instructions cycle-time after occurring the interrupt request.
(14) Subroutine stack levels
- 128 levels (Max.): Stack area included in RAM area (15) Multiplication and division
16-bit × 8-bit (7 instruction cycle times) 16-bit / 8-bit (7 instruction cycle times) (16) Three oscillation circuits
- On-chip RC oscillation circuit using for the system clock. - On-chip CF oscillation circuit using for the system clock.
- On-chip crystal oscillation circuit using for the system clock and for time-ba clock. (17) Standby function
- HALT mode function
The HALT mode is ud to reduce power dissipation. In this operation mode, program execution is stopped. This operation mode can be relead by interrupt request signals or the initial system ret request signal. - HOLD mode function
The HOLD mode is ud to freeze all the oscillations;
RC (internal), CF and Crystal oscillations. This mode can be relead by the following operations. • Ret terminal (RES ) t to Low level
• P70/INT0/T0IN, P71/INT1/T0IN terminals t to assigned level (programmable) • Input a Port 0 interrupt condition
(18) Factory shipment
• QFP80E delivery form
(19) Development support tools
Evaluation (EVA) chip : LC866097 EPROM version : LC86E6449 One time version : LC86P6449 Emulator : EVA-86000 + ECB866400 (Evaluation chip board) + POD866400 (POD)
Notice for u
1. Set VDD=4.0V to 6.0V at using S16 to S37 as input port.
2. Follow the under table.
Frequency range of the system clock Voltage range Clock Divider Note
15kHz to 30kHz 1/1 Can not u 1/2 divider
30kHz to 6MHz 4.5V to 6.0V 1/1,1/2
15kHz to 30kHz 1/1 Can not u 1/2 divider
30kHz to 1.5MHz 1/1,1/2 1.5MHz to 3MHz 2.5V to 6.0V 1/2 Can not u 1/1 divider 4.5V to 6.0V 1/1,1/2
Internal RC oscillation 2.5V to 6.0V 1/2 Can not u 1/1 divider
Pin Assignment
QIP80E
Package Dimension (unit : mm)
3174
SANYO : QIP-80E
P00 P01 P02 P03 P04 P05 P06 P07 VSS2 P10/SO0 P11/SI0/SB0 P12/SCK0 P13/SO1 P14/SI1/SB1 P15/SCK1 P16/BUZ S15/T15 S14/T14 S13/T13 S12/T12 S11/T11 S10/T10 S9/T9 S8/T8 S7/T7 S6/T6 S5/T5 S4/T4 S3/T3 S2/T2 S1/T1 S0/T0
P 17/P W M 0P 30P 31P 32P 33P 70/I N T 0R E S X T 1/P 74X T 2/P 75V S S 1C F 1C F 2V D D 1P 80/A N 0P 81/A N 1P 82/A N 2P 83/A N 3P 84/A N 4P 85/A N 5P 86/A N 6P 87/A N 7P 71/I N T 1P 72/I N T 2/T 0I N P 73/I N T 3/T 0I N
S 37/P E 5 S 36/P E 4 S 35/P E 3 S 34/P E 2 S 33/P E 1 S 32/P E 0 S 31/P D 7 S 30/P D 6 S 29/P D 5 S 28/P D 4 S 27/P D 3 S 26/P D 2 S 25/P D 1 S 24/P D 0 S 23/P C 7 S 22/P C 6 S 21/P C 5 S 20/P C 4 S 19/P C 3 S 18/P C 2 S 17/P C 1 S 16/P C 0 V P V D D 2
65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
朋友圈评论1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1617 18 19 20 21 22 23 24
偷鸡摸狗是什么意思64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
System Block Diagram
