DATA SHEET
SKY72301-22: Spur-Free, 1.0 GHz Dual Fractional-N Frequency Synthesizer
Applications
•General purpo RF systems
•Low bit rate wireless telemetry
•Instrumentation
•Specialized Mobile Radios (SMRs) and Private Mobile Radios
(PMRs)
Features
•Spur-free operation
•1.0 GHz maximum operating frequency
•500 MHz maximum auxiliary synthesizer
•Ultra-small step size, 100 Hz or less
•High internal reference frequency enables large loop bandwidth
implementations
•Very fast switching speed (e.g., below 100 µs)
•Pha noi to –96 dBc/Hz inside the loop filter bandwidth
@ 950 MHz
•Software programmable power-down modes
•High-speed rial interface up to 100 Mbps
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•Three-wire programming
•Programmable division ratios on reference frequency
•Pha detectors with programmable gain provide a
programmable loop bandwidth
•Frequency power steering further enhances rapid acquistion
time
•On-chip crystal oscillator
•Frequency adjust for temperature compensation
•Direct digital modulation
•3 V operation
Skyworks offers lead (Pb)-free, RoHS (Restriction of
Hazardous Substances) compliant packaging.
•5 V output to loop filter
•EP-TSSOP (28-pin, 9.7 x 6.4 x 1.1 mm) Pb-free (MSL3, 260 °C
per JEDEC J-STD-020) package
Description
Skyworks SKY72301-22 direct digital modulation fractional-N
frequency synthesizer provides ultra-fine frequency resolution,
fast switching speed, and low pha-noi performance. This
synthesizer is a key building block for high-performance radio
system designs that require low power and fine step size.
The ultra-fine step size of less than 100 Hz allows this synthesizer
to be ud in very narrowband wireless applications. With proper
temperature nsing or through control channels, the
synthesizer’s fine step size can compensate for crystal oscillator
or Intermediate Frequency (IF) filter drift. As a result, crystal
oscillators or crystals can replace temperature- compensated or
ovenized crystal oscillators, reducing parts count and associated
component cost. The device’s fine step size can also be ud for
Doppler shift corrections.
The SKY72301-22 has a pha noi floor of –95 dBc/Hz up to
1.0 GHz operation as measured inside the loop bandwidth. This is
permitted by the on-chip low noi dividers and low divide ratios
provided by the device’s high fractionality.
Reference crystals or oscillators up to 50 MHz can be ud with
the SKY72301-22. The crystal frequency is divided down by
十加走之旁independent programmable divider ratios of 1 to 32 for the main
and auxiliary synthesizers. The pha detectors can operate at a
maximum speed of 25 MHz, which allows better pha noi due
to the lower division value. With a high reference frequency, the
loop bandwidths can also be incread. Larger loop bandwidths
improve the ttling times and reduce in-band pha noi.
Therefore, typical switching times of less than 100 µs can be
achieved. The lower in-band pha noi also permits the u of
lower cost Voltage Controlled Oscillators (VCOs) in customer
applications.
The SKY72301-22 has a frequency power steering circuit that
helps the loop filter steer the VCO when the frequency is too fast
or too slow, further enhancing acquisition time.
DATA SHEET • SKY72301-22 FREQUENCY SYNTHESIZER
The unit operates with a three-wire, high-speed rial interface. A combination of a large bandwidth, fine resolution, and the three-wire, high-speed rial interface allows for a direct frequency modulation of the VCO. This supports any continuous pha, constant envelope modulation scheme such as Frequency Modulation (FM), Frequency Shift Keying (FSK), Minimum Shift Keying (MSK), or Gaussian Minimum Shift Keying (GMSK).
The capability to support such modulation schemes eliminates the need for In-Pha and Quadrature (I/Q) Digital-To-Analog
Converters (DACs), quadrature upconverters, and IF filters from the transmitter portion of the radio system.
Figure 1 shows a functional block diagram for the SKY72301-22. The device package and pinout for the 28-pin Expod Pad Thin
Shrink Small Outline Package (EP-TSSOP) are shown in Figure 2.
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Figure 1. SKY72301-22 Functional Block Diagram
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1234567891011121314
2827262524232221201918171615
Clock Mod_in Mux_out VSUBdigital GNDcml VCCcml_main Fvco_main Fvco_main LD/PSmain VCCcp_main CPout_main GNDcp_main Xtalacgnd/OSC
Xtalin/OSC
CS Data VCCdigital GNDdigital VCCcml_aux VCCvco_aux Fvco_aux GNDcp_aux CPout_aux VCCcp_aux LD/PSaux GNDxtal VCCxtal Xtalout/NC
Figure 2. SKY72301-22 Pinout, 28-Pin EP-TSSOP
(Top View)
DATA SHEET • SKY72301-22 FREQUENCY SYNTHESIZER
Technical Description
The SKY72301-22 is a fractional-N frequency synthesizer using a ∆Σ modulation technique. The fractional-N implementation provides low in-band noi by having a low division ratio and fast frequency ttling time. In addition, the SKY72301-22 provides arbitrarily fine frequency resolution with a digital word, so that the frequency synthesizer can be ud to compensate for crystal frequency drift in the RF transceiver.
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The rial interface is a versatile three-wire interface consisting of three pins: Clock (rial clock), Data (rial input), and CS (chip lect). It enables the SKY72301-22 to operate in a system where one or multiple masters and slaves are prent. To perform a loopback test at start-up and to check the integrity of the board and processor, the rial data is fed back to the master device (e.g., a microcontroller or microprocessor unit) through a programmable multiplexer. This facilitates hardware and software debugging.
Registers
There are ten 16-bit registers in the SKY72301-22. For more information, e the Register Descriptions ction of this document.
Main and Auxiliary ∆Σ Modulators
The fractionality of the SKY72301-22 is accomplished by the u of a proprietary, configurable 10-bit or 18-bit ∆Σ modulator for the main synthesizer and 10-bit ∆Σ modulator for the auxiliary synthesizer.
Main and Auxiliary Fractional Units
The SKY72301-22 provides fractionality through the u of main and auxiliary ∆Σ modulators. The output from the modulators is combined with the main and auxiliary divider ratios through their respective fractional units.
VCO Prescalers
The VCO prescalers provide low-noi signal conditioning of the VCO signals. They translate from an off-chip, single-ended or differential signal to an on-chip differential Current Mode Logic (CML) signal. The SKY72301-22 has independent main and auxiliary VCO prescalers.
Main and Auxiliary VCO Dividers
The SKY72301-22 provides programmable dividers that control the CML prescalers and supply the required signals to the charge pump pha detectors. Programmable divide ratios ranging from 38 to 537 are possible in fractional-N mode and from 32 to 543 in integer-N mode.
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Reference Frequency Oscillator
The SKY72301-22 has a lf-contained, low-noi crystal oscillator. This crystal oscillator is followed by the clock generation circuitry that generates the required clock for the programmable reference frequency dividers.
Reference Frequency Dividers
The crystal oscillator signal can be divided by a ratio of 1 to 32 to create the reference frequencies for the pha detectors. The SKY72301-22 has both a main and an auxiliary frequency synthesizer, and provides independently configurable dividers of the crystal oscillator frequency for both the main and auxiliary pha detectors. The divide ratios are programmed by the Reference Frequency Dividers Register.
NOTE: The divided crystal oscillator frequencies (which are the internal reference frequencies), Fref_main and Fref_aux,
are referred to as the reference frequencies throughout
this document.
Pha Detectors and Charge Pumps
The SKY72301-22 us a parate charge pump pha detector for each synthesizer which provides a programmable gain, Kd, from 31.25 to 1000 µA/2π radians in 32 steps programmed using the Pha Detector/Charge Pumps Control Register. Frequency Steering
When programmed for frequency power steering, the SKY72301-22 has a circuit that helps the loop filter steer the VCO using the LD/PSmain signal (pin 9). In this configuration, the LD/PSmain signal can provide a more rapid acquisition.
When programmed for lock detection, internal frequency steering is implemented and provides frequency acquisition times comparable to conventional pha/frequency detectors.
Lock Detection
When programmed for lock detection, the SKY72301-22 provides an active low, pulsing open collect
or output using the LD/PSmain signal (pin 9) to indicate the out-of-lock condition. When locked, the LD/PSmain signal is tri-stated (high impedance).
Power Down
The SKY72301-22 supports a number of power-down modes through the rial interface. For more information, e the Register Descriptions ction of this document.
DATA SHEET • SKY72301-22 FREQUENCY SYNTHESIZER
Serial Interface Operation
The rial interface consists of three signals: Clock (pin 1), Data (pin 27) and CS (pin 28). The Clock signal controls data on the two rial data lines (Data and CS). The Data pin bits shift into a
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temporary register on the rising edge of Clock. The CS line allows individual lection transfers that synchronize and sample the information of slave devices on the same bus.
Figure 3 functionally depicts how a rial transfer takes place. A rial transfer is initiated when a microcontroller or
microprocessor forces the CS line to a low state. This is followed immediately by an address/data stream nt to the Data pin that coincides with the rising edges of the clock prented on the Clock line.
Each rising edge of the Clock signal shifts in one bit of data on the Data line into a shift register. At the same time, one bit of data is shifted out of the Mux_out pin (if the rial bit stream is lected) at each falling edge of Clock. To load any of the registers, 16 bits of address or data must be prented to the Data line with the LSB last while the CS signal is low. If the CS signal is low for more than 16 clock cycles, only the last address or data bits are ud to load the registers.
If the CS signal is brought to a high state before the 13th Clock edge, the bit stream is assumed to be modulation data samples. In this ca, it is assumed that no address bits are prent and that all the bits in the stream should be loaded into the Modulation Data Register.
Register Programming
Register programming equations, described in this ction, u the following variables and constants: N fractional
Desired VCO division ratio in fractional-N applications. This is a real number and can be interpreted as the reference frequency (F ref ) multiplying factor such that the resulting frequency is equal to the desired VCO frequency.
N integer
Desired VCO division ratio in integer-N applications. This number is an integer and can be interpreted as the reference frequency (F ref ) multiplying factor so that the resulting frequency is equal to the desired VCO frequency.
N reg
Nine-bit unsigned input value to the divider ranging from 0 to 511 (integer-N mode) and from 6 to 505 (fractional-N mode).
divider
北京爆肚This constant equals 262144 when the ∆Σ modulator is in 18-bit mode, and 1024 when the ∆Σ modulator is in 10-bit mode.
dividend When in 18-bit mode, this is the 18-bit signed input
value to the ∆Σ modulator, ranging from
–131072 to +131071 and providing 262144 steps, each step equal to F div_ref /218 Hz.
When in 10-bit mode, this is the 10-bit signed input value to the ∆Σ modulator, ranging from
–512 to +511 and providing 1024 steps, each step equal to Fdiv_ref /210 Hz.
F VCO Desired VCO frequency (either F vco_main or F vco_aux ). F div_ref Divided reference frequency prented to the pha detector (either F ref_main or F ref_aux ).
X A3A2A1A0D11D10D9D8D7D6D5D4D3D2D1D0XXX
Clock
Last
Data CS
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Figure 3. Serial Transfer Timing Diagram
DATA SHEET • SKY72301-22 FREQUENCY SYNTHESIZER
Fractional-N Applications. The desired division ratio for the
main and auxiliary synthesizer is given by the following equation:
where N fractional must be between 37.5 and 537.5.
The value to be programmed by the Main or Auxiliary Divider
Register is given by the equation:
NOTE: The Round function rounds the number to the nearest integer.
When in fractional mode, allowed values for N reg are from 6 to 505, inclusive.
The value to be programmed by either of the MSB/LSB Dividend registers or the Auxiliary Dividend Register is given by the
following equation:
where the divider is either 1024 in 10-bit mode or 262144 in
18-bit mode. Therefore, the dividend is a signed binary value either 10 or 18 bits long.
NOTE: Becau of the high fractionality of the SKY72301-22, there is no practical need for any integer relationship
between the reference frequency and the channel spacing
or desired VCO frequencies.
Sample calculations for two fractional-N applications are provided in Figure 4.
Integer-N Applications. The desired division ratio for the main or红色朗诵稿件
auxiliary synthesizer is given by:
where N integer is an integer number from 32 to 543.
The value to be programmed by the Main or Auxiliary Divider
Register is given by the following equation:
When in integer mode, allowed values for N reg are from 0 to 511 for both the main and auxiliary synthesizers.
NOTE: As with all integer-N synthesizers, the minimum step size is related to the crystal frequency and reference frequency
division ratio. A sample calculation for an integer-N application is provided in Figure 5.
Register Loading Order. In applications where the main synthesizer is in 18-bit mode, the Main Dividend MSB Register holds the 10 MSBs of the dividend and the Main Dividend LSB Register holds the8 LSBs of the dividend. The registers that control the main synthesizer’s divide ratio are to be loaded in the following order:
•Main Divider Register
•Main Dividend LSB Register
•Main Dividend MSB Register (at which point the new divide ratio takes effect)
In applications where the main synthesizer is in 10-bit mode, the Main Dividend Register holds the 10 bits of the dividend. The registers that control the main synthesizer’s divide ratio are to be loaded in the following order:
•Main Divider Register
•Main Dividend MSB Register (at which point the new divide ratio takes effect)
For the auxiliary synthesizer, the Auxiliary Dividend Register holds the 10 bits of the dividend. The registers that control the auxiliary synthesizer’s divide ratio are to be loaded in the following order: •Auxiliary Divider Register
•Auxiliary Dividend Register (at which point the new divide ratio takes effect)
NOTE: When in integer mode, the new divide ratios take effect when the Main or Auxiliary Divider Register is loaded. Direct Digital Modulation
The high fractionality and small step size of the SKY72301-22 allow the VCO to be tuned to practically any frequency in the VCO’s operating range. This allows direct digital modulation by programming the different desired frequencies at preci instants. Typically, the channel frequency is programmed by the Main Divider and MSB/LSB Dividend registers, and the instantaneous frequency offt from the carrier is programmed by the Modulation Data Register.
The Modulation Data Register can be accesd in three ways as defined in the following subctions.
DATA SHEET • SKY72301-22 FREQUENCY SYNTHESIZER
斯苗儿Ca 1: To achieve a desired F vco_main frequency of 902.4530 MHz using a crystal frequency of 40 MHz with operation of the synthesizer in 18-bit mode. Since the maximum internal reference frequency (F div_ref) is 25 MHz, the crystal
frequency is divided by 2 to obtain a F div_ref of 20 MHz. Therefore:
N fractional = F vco_main
F div_ref
902.4530
=
20
45.12265
=
The value to be programmed in the Main Divider Register is:
N reg = Round[N fractional] – 32
32
–
=
Round[45.12265]
= 45 – 32
(decimal)
=
13
(binary)
=
000001101
With the modulator in 18-bit mode, the value to be programmed in the Main Dividend Registers is:
×
(N fractional– N reg – 32)]
=
Round[divider
dividend
= Round[262144 × (45.12265 – 13 – 32)]
×
(0.12265)]
=
Round[262144
Round[32151.9616]
=
(decimal)
32152
=
(binary)
=
000111110110011000
where 00 0111 1101 is loaded in the MSB of the Main Dividend Register and 1001 1000 is loaded in the LSB of the
Main Dividend Register.
Summary:
·Main Divider Register = 0 0000 1101
·Main Dividend Register, LSB = 1001 1000
·Main Dividend Register, MSB = 00 0111 1101
·The resulting main VCO frequency is 902.453 MHz
·Step size is 76.3 Hz
Note: The frequency step size for this ca is 20 MHz divided by 218, giving 76.3 Hz.
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Figure 4. Fractional-N Applications: Sample Calculation (1 of 2)
