•Intel Agilex Device Family Pin Connection Guidelines
4.1.1. QSF Assignments for Reference Clock Pins
Refer to the Device Family Pin Connection Guidelines for how to connect unud
reference clock pins.
Table 53.QSF Assignments for a Single Reference Clock Pin (refclk[0])
You must manually include the QSF ttings for every ud reference clock pin.
Description Value QSF Assignment
西游记阅读感受
Set reference clock IO standard differential LVPECL t_instance_assignment -name IO_STANDARD "DIFFERENTIAL
一生只爱一个人
LVPECL" -to <refclk_name> -entity <block_name>
Enable on-die termination resistors enable_term = (on-chip
termination on)
想念的话
disable_term = (on-
chip termination off)
t_instance_assignment -name HSSI_PARAMETER
"refclk_divider_enable_termination=enable_term" -to
ref_clk[0]
Recommendation: Set this to
enable_term unless external on-board
termination is ud and internal termination is suppod to be bypasd.
Select 3.3 V
tolerant
instead of 2.5
V
enable_3p3v_tol =
(3.3V)
disable_3p3v_tol =
(2.5V)
t_instance_assignment -name HSSI_PARAMETER
"refclk_divider_enable_3p3v=enable_3p3v_tol" -to
ref_clk[0](33)
Recommendation: Set this to disable_3p3v_tol unless the clock source
is compliant to LVPECL 3.3v standard.
Enable LVPECL
driver
hysteresis带颜色的歌词
enable_hyst =
(hysteresis on)
空调除湿图标disable_hyst =
(hysteresis off)
t_instance_assignment -name HSSI_PARAMETER
"refclk_divider_disable_hysteresis=enable_hyst" -to
ref_clk[0]
苹果醋怎么喝Recommendation: Set this to disable_hyst provided that the reference
clock characteristic meets the specification in the Device Data Sheet.
Set reference
clock
frequency
freq_in_Hz = "legal
value"
t_instance_assignment -name HSSI_PARAMETER
"refclk_divider_input_freq=freq_in_Hz" -to ref_clk[0]
Recommendation: U the same reference clock frequency number as in the
respective transceiver IP.
Power down
LVPECL driver
刘墉女儿fal = (driver on)
true = (driver off)
t_instance_assignment -name HSSI_PARAMETER
"refclk_divider_powerdown_mode=fal" -to ref_clk[0]
Recommendation: If you plan to u the target reference clock, t this to
fal.f开头的英文单词
Related Information
•Intel Stratix 10 Device Data Sheet
•Intel Stratix 10 Device Family Pin Connection Guidelines
•Intel Agilex Device Data Sheet
•Intel Agilex Device Family Pin Connection Guidelines
(33)Refer to the Device Data Sheet for the reference clock voltage rating electrical specifications.
(34)Refer to the Device Data Sheet for the reference clock frequency specification.
4.Clock Network
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Figure 64.IO Pad Ring - Transceiver Reference Clock Input Pad
REFCLK REFCLK_N
0.5 V (2.5 V LVPECL)1.3 V 0.5 V (2.5 V LVPECL)E-tile completes the device configuration successfully provided that a valid reference clock frequency, 125 MHz - 500 MHz (if the refclk Divide by 2 is disabled) or 250MHz - 700 MHz (if the refclk Divide by 2
is enabled), is available during device configuration, which may or may not be the same as what is configured in the
transceiver IP . A difference in the configured refclk in the IP compared to the available refclk on the board can cau unexpected transitions on the E-tile TX output.
Make sure you are okay with this behavior until the refclk frequencies are t
correctly followed by the recommended ret and device configuration steps as per PMA Analog Ret . If the unexpected transitions are not acceptable, you can disable the transceiver TX output by writing the attribute code 0x0001 with data 0x0003 after device configuration. The E-tile TX may still give some unexpected transitions between the device configuration pha until the attribute code 0x0001 is written.
After correctly configuring back the on-board reference clock, follow the recommended ret and device configuration steps as per PMA Analog Ret to ret the internal controller . Refer to the Register Map for more details on attribute codes and data. Not having a stable reference clock during device configuration caus the configuration to fail.
4.Clock Network
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Figure 65.REFCLK LVPECL Pins
For details on LVPECL standard spec, refer to Device Data Sheet .
Related Information
•
QSF Assignments for Reference Clock Pins on page 119•
PMA Analog Ret on page 138•
Register Map on page 217•
Pin-Out Files for Intel FPGA Devices •
Intel Stratix 10 Device Data Sheet •
Intel Stratix 10 Device Family Pin Connection Guidelines •Intel Agilex Device Data Sheet
4.Clock Network
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