High Resolution 6 GHz Fractional-N
Frequency Synthesizer
Data Sheet
ADF4157
Rev. D
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FEATURES
伤心诗句
RF bandwidth to 6 GHz
25-bit fixed modulus allows subhertz frequency resolution 2.7 V to 3.3 V power supply
Separate V P allows extended tuning voltage Programmable charge pump currents 3-wire rial interface Digital lock detect Power-down mode
Pin compatible with the following frequency synthesizers: ADF4110/ADF4111/ADF4112/ADF4113/ ADF4106/ADF4153/ADF4154/ADF4156 Cycle slip reduction for faster lock times
APPLICATIONS
Satellite communications terminals, radar equipment Instrumentation equipment Personal mobile radio (PMR) Ba stations for mobile radio Wireless handts
GENERAL DESCRIPTION
The ADF4157 is a 6 GHz fractional-N frequency synthesizer with a 25-bit fixed modulus, allowing subhertz frequency resolution at 6 GHz. It consists of a low noi digital pha frequency detector (PFD), a precision charge pump, and a programmable reference divider. There is a Σ-Δ bad fractio
nal interpolator to allow programmable fractional-N division. The INT and FRAC values define an overall N divider, N = INT + (FRAC/225). The ADF4157 features cycle slip reduction circuitry, which leads to faster lock times without the need for modifications to the loop filter. Control of all on-chip registers is via a simple 3-wire interface. The device operates with a power supply ranging from 2.7 V to 3.3 V and can be powered down when not in u.
FUNCTIONAL BLOCK DIAGRAM
DATA
LE
CLK REF IN
IN A IN B
MUXOUT
捆绑英语05874-001
Figure 1.
整蛊室友
ADF4157
Data Sheet
Rev. D | Page 2 of 24
TABLE OF CONTENTS
Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 Timing Specifications .................................................................. 4 Absolute Maximum Ratings ............................................................ 5 Thermal Resistance ...................................................................... 5 ESD Caution .................................................................................. 5 Pin Configurations and Function Descriptions ........................... 6 Typical Performance Characteristics ............................................. 8 Circuit Description ........................................................................... 9 Reference Input Section ............................................................... 9 RF Input Stage ............................................................................... 9 RF INT Divider ............................................................................. 9 25-Bit Fixed Modulus .................................................................. 9 INT, FRAC, and R Relationship ................................................. 9 RF R Counter ................................................................................ 9
Pha Frequency Detector (PFD) and Charge Pump ............ 10 MUXOUT and Lock Detect ...................................................... 10 Input Shift Register (10)
Program Modes .......................................................................... 10 Register Maps .................................................................................. 11 FRAC/INT Register (R0) 12 LSB FRAC Register (R1) Map .................................................. 13 R Divider Register (R2) Map .................................................... 14 Function Register (R3) Map ..................................................... 16 Test Register (R4) Map .............................................................. 17 Applications Information .............................................................. 18 Initialization Sequence .............................................................. 18 RF Synthesizer: A Worked Example ........................................ 18 Reference Doubler and Reference Divider ............................. 18 Cycle Slip Reduction for Faster Lock Times ........................... 18 Fastlock Timer and Register Sequences .................................. 19 Fastlock: An Example ................................................................ 19 Fastlock: Loop Filter Topology ................................................. 19 Spur Mechanisms ....................................................................... 19 Low Frequency Applications .................................................... 20 Filter Design—ADIsimPLL ....................................................... 2
0 Operating with Wide Loop Filter Bandwidths ....................... 20 PCB Design Guidelines for the Chip Scale Package .............. 20 Outline Dimensions ....................................................................... 21 Ordering Guide .. (21)
REVISION HISTORY
8/12—Rev. C to Rev. D
Changes to Figure 4 and Table 5 (6)
Updated Outline Dimensions (Changed CP-20-1 to CP-20-6) ..... 22 Changes to Ordering Guide ........................................................... 21 Criticizing
3/12—Rev. B to Rev. C
Changes to Table 1 ............................................................................ 3 Changes to Ordering Guide .......................................................... 21 9/11—Rev. A to Rev. B
Changes to Noi Characteristics Parameter ................................ 3 Changes to EPAD Note .................................................................... 6 1/09—Rev. 0 to Rev. A
Changes to Figure 1 .......................................................................... 1 Changes to Reference Characteristics Parameter, Table 1 .......... 3 Changes to Table 3 . (5)
Changes to Figure 4 and Table 5 ...................................................... 6 Changes to Figure 15 ...................................................................... 10 Changes to Figure 16 ...................................................................... 11 Changes to Figure 17 ...................................................................... 12 Changes to Figure 19 ...................................................................... 15 Added Negative Bleed Current Section, CLK Divider Mode Section, and 12-Bit Clock Divider . 17 Changes to Rerved Bits Section and Figure 21 ....................... 17 Deleted Interfacing Section ........................................................... 18 Added Fastlock Timer and Register Sequences Section, Fastlock: An Example Section, and Fastlock: Loop Filter
Topology Section ............................................................................ 19 Added Figure 22 and Figure 23; Renumbered Sequentially ..... 19 Added Operating with Wide Loop Filter Bandwidths
Section .............................................................................................. 20 Updated Outline Dimensions ....................................................... 21 7/07—Revision 0: Initial Version
Data Sheet
ADF4157
Rev. D | Page 3 of 24
SPECIFICATIONS
AV DD = DV DD = 2.7 V to 3.3 V; V P = AV DD to 5.5 V; AGND = DGND = 0 V; T A = T MIN to T MAX , unless otherwi noted; dBm referred to 50 Ω. Table 1.
Parameter
B Version 1 Unit Test Conditions/Comments RF CHARACTERISTICS (3 V)
RF Input Frequency (RF IN ) 0.5/6.0 GHz min/max −10 dBm/0 dBm min/max; for lower frequencies, ensure slew rate (SR) > 400 V/µs REFERENCE CHARACTERISTICS
REF IN Input Frequency 10/300 MHz min/max For f REFIN < 10 MHz, ensure slew rate > 50 V/µs REF IN Input Sensitivity 0.4/AV DD V p-p min/max For 10 MHz < f REFIN < 250 MHz, biad at AV DD /22
0.7/AV DD V p-p min/max For 250 MHz < f REFIN < 300 MHz, biad at AV DD /22 REF IN Input Capacitance 10 pF max REF IN Input Current ±100 µA max PHASE DETECTOR
Pha Detector Frequency 3 32 MHz max CHARGE PUMP
I CP Sink/Source
Programmable High Value 5 mA typ With R SET = 5.1 kΩ Low Value
312.5 µA typ
Absolute Accuracy 2.5 % typ
With R SET = 5.1 kΩ R SET Range
2.7/10 kΩ min/max
I CP Three-State Leakage Current 1 nA typ Sink and source current Matching 2 % typ 0.5 V < V CP < V P – 0.5 I CP vs. V CP
2 % typ 0.5 V < V CP < V P – 0.5 I CP vs. Temperature 2 % typ V CP = V P /2 LOGIC INPUTS
V INH , Input High Voltage 1.4 V min V INL , Input Low Voltage 0.6 V max I INH /I INL , Input Current ±1 µA max C IN , Input Capacitance 10 pF max LOGIC OUTPUTS
V OH , Output High Voltage 1.4
筱懿
V min Open-drain 1 kΩ pull-up to 1.8 V V OH , Output High Voltage VDD – 0.4 V min CMOS output chon V OL , Output Low Voltage 0.4 V max I OL = 500 µA POWER SUPPLIES
AV DD 2.7/3.3 V min/max DV DD AV DD
V P AV DD /5.5 V min/V max
I DD
29 mA max 23 mA typical Low Power Sleep Mode 10 µA typ NOISE CHARACTERISTICS
Normalized Pha Noi Floor (PN SYNTH )4
−211 dBc/Hz typ PLL loop B/W = 500 kHz; measured at 100 kHz
Normalized 1/f Noi (PN 1_f )5 −110 dBc/Hz typ 10 kHz offt; normalized to 1 GHz Pha Noi Fl
oor 6 −137 dBc/Hz typ @ 10 MHz PFD frequency
−133 dBc/Hz typ @ 25 MHz PFD frequency Pha Noi Performance 7
@ VCO output
5800 MHz Output 8
−87
dBc/Hz typ @ 2 kHz offt, 25 MHz PFD frequency
1 Operating temperature of B version is −40°C to +85°C. 2
AC-coupling ensures AV DD /2 bias. 3
Guaranteed by design. Sample tested to ensure compliance. 4
The synthesizer pha noi floor is estimated by measuring the in-band pha noi at the output of the VCO and subtracting 20 log(N) (where N is the N divider value) and 10 log(F PFD ). PN SYNTH = PN TOT − 10 log(F PFD ) − 20 log(N). 5
The PLL pha noi is compod of 1/f (flicker) noi plus the normalized PLL noi floor. The formula for calculating the 1/f noi contribution at an RF frequency, F RF , and at a frequency offt f is given by PN = PN 1_f + 10 log(10 kHz/f) + 20 log(F RF /1 GHz). Both the normalized pha noi floor and flicker noi are modeled in ADIsimPLL. 6
The synthesizer pha noi floor is estimated by measuring the in-band pha noi at the output of the VCO and subtracting 20logN (where N is the N divider value). 7
The pha noi is measured with the EV-ADF4157SD1Z and the Agilent E5052A pha noi system. 8
f REFIN = 100 MHz; f PFD = 25 MHz; offt frequency = 2 kHz; RF OUT = 5800.25 MHz; N = 232; loop bandwidth = 20 kHz.
ADF4157
Data Sheet
Rev. D | Page 4 of 24
TIMING SPECIFICATIONS
AV DD = DV DD = 2.7 V to 3.3 V; V P = AV DD to 5.5 V; AGND = DGND = 0 V; T A = T MIN to T MAX , unless otherwi noted; dBm referred to 50 Ω. Table 2.
远大学校
Parameter Limit at T MIN to T MAX (B Version) Unit Test Conditions/Comments t 1 20 ns min LE tup time
t 2 10 ns min Data to clock tup time t 3 10 ns min Data to clock hold time t 4 25 ns min Clock high duration t 5 25 ns min Clock low duration t 6 10 ns min Clock to LE tup time t 7
20
ns min
LE pul width
CLK
DATA
LE
LE
05874-002
Figure 2. Timing Diagram
Data Sheet
ADF4157
Rev. D | Page 5 of 24
well的意思ABSOLUTE MAXIMUM RATINGS
T A = 25°C, GND = AGND = DGND = 0 V , V DD = AV DD = DV DD , unless otherwi noted. Table 3.
如何和异性聊天Parameter
Rating
AV DD /DV DD to AGND/DGND −0.3 V to +4 V AV DD to DV DD
−0.3 V to +0.3 V V P to AGND/DGND −0.3 V to +5.8 V V P to AV DD /DV DD
−0.3 V to +5.8 V Digital I/O Voltage to AGND/DGND −0.3 V to V DD + 0.3 V Analog I/O Voltage to AGND/DGND −0.3 V to V DD + 0.3 V REF IN , RF IN x to AGND/DGND −0.3 V to V DD + 0.3 V Operating Temperature Range
Industrial (B Version)
−40°C to +85°C Storage Temperature Range
−65°C to +125°C Maximum Junction Temperature 150°C Reflow Soldering
Peak Temperature
260°C Time at Peak Temperature
40 c
Stress above tho listed under Absolute Maximum Ratings may cau permanent damage to the device. This is a stress rating only; functional operation of the device at the or any other conditions above tho indicated in the operational
ction of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL RESISTANCE
θJA is specified for the worst-ca conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 4. Thermal Resistance
Package Type θJA Unit TSSOP
112 °C/W LFCSP (Paddle Soldered)
30.4
°C/W
ESD CAUTION
ADF4157
Data Sheet
Rev. D | Page 6 of 24
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
CP CPGND AGND AV DD RF IN A RF IN B R SET DV DD MUXOUT LE
CE REF IN
DGND
CLK DATA V P 05874-003
Figure 3. TSSOP Pin Configuration
05874-004
NOTES
1. IT IS RECOMMENDED THAT THE EXPOSED PAD BE THERMALLY CONNECTED TO A COPPER
PLANE FOR ENHANCED THERMAL PERFORMANCE. THIS PAD SHOULD BE CONNECTED TO AGND.
LE MUXOUT
DATA CLK CE
CPGND AGND AGND RF IN B RF IN A A V D D A V D D R E F I N D G N D 1D G N D 9R S E T
0C P
8V P
7D V D D停停当当
6D V D D
Figure 4. LFCSP Pin Configuration
