Debouncer（消抖） - The solution
One solution would be to add an R/C hardware filter（过滤）, and u a Schmitt-trigger（施密特触发器） gate to feed the FPGA.
But there is a simpler solution.
FPGA filter
韩存保FPGAs are great at simple arithmetic(算术). Let's u a counter in the FPGA to e how long the push-button is pushed or relead. Only once the counter is maxed-out（最大化）, we decide that the push-button has changed state.
PB is the push-button signal (active low in this example). It may contain glitches（小故障）, and is asynchronous（异步的） to any clock. So it is mostly unusable as it is.
We are going to synchronize（同步） PB to a clock (20MHz in this example) and then create three push-buttons outputs, glitch free, synchronous健身语录（同步） to the clock. Each output will be active high and indicate a different condition of the push-button (push-button state, just pushed, just relead).
module PushButton_Debouncer(
input clk,
input PB, // "PB" is the glitchy, asynchronous（异步） to clk, active low push-button signal
// from which we make three outputs, all synchronous（同步） to the clock
output reg PB_state, // 1 as long as the push-button is active (down)
output PB_down, // 1 for one clock cycle when the push-button goes down (i.e. just pushed)
output PB_up // 1 for one clock cycle when the push-button goes up (i.e. just relead)
);
// First u two flip-flops to synchronize（同步） the PB signal the "clk" clock domain南海冲突（域）
reg PB_sync_0; always @(250字podge clk) PB_sync_0 <= ~PB; // invert（转化） PB to make PB_sync_0 active high
reg鲜肉粽子的做法 PB_sync_1; always @(podge clk) PB_sync_1 <= PB_sync_0;
// Next declare a 16-bits counter
公鸡打架reg [15:0] PB_cnt;
// When the push-button is pushed or relead, we increment（增加） the counter
// The counter has to be maxed out before we decide that the push-button state has changed
wire PB_idle = (PB_state==PB_sync_1);
wire PB_cnt_max = &PB_cnt; // true when all bits of PB_cnt are 1's
always @(podge clk)
if(PB_idle)入党申请书
PB_cnt <= 0; // nothing's going on
el
begin
PB_cnt <= PB_cnt + 16'd1; // something's going on, increment the counter
读书笔记三年级if(PB_cnt_max) PB_state <= ~PB_state; // if the counter is maxed out, PB changed!
end
assign PB_down = ~PB_idle & PB_cnt_max & ~PB_state;
assign PB_up = ~PB_idle & PB_cnt_max & PB_state;
endmodule
We ud a 16-bits counter. With a 20MHz system clock, it would take 3ms to max-out. From the ur's perspective, 3ms is instantaneous（即使的）. But the glitches（小故障） are gone. Depending on how glitchy your push-button is and your system clock speed, you might need to adjust the counter width.
Your turn to experiment!
