CXD2529Q
CD Digital Signal Processor
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Playback speed CD-DSP block
DAC block × 2 3.4V 4.5V × 1 3.4V 3.4V
× 1∗1
3.4V
V DD (min.) [V]
100 pin QFP (Plastic)
Description
The CXD2529Q is a digital signal processor LSI for CD players and is equipped with built-in digital filters,zero detection circuit, 1-bit DAC, and analog low-pass filter on a single chip.
Features
Digital Signal Processor (DSP) Block
•Playback mode supporting CAV (Constant Angular Velocity)
–Frame jitter-free
–Allows 0.5 to double-speed continuous playback –Allows relative rotational velocity readout –Supports external spindle control •Wide capture range mode
–Spindle rotational velocity following method
–Supports normal-speed and double-speed playback •16K RAM
•EFM data demodulation
•Enhanced EFM frame sync signal protection •SEC strategy-bad error correction
•Subcode demodulation and Sub Q data error detection •Digital spindle rvo •16-bit traver counter
•Asymmetry compensation circuit •Serial bus-bad CPU interface
•Error correction monitor signals, etc. are output from a new CPU interface.•Servo auto quencer
•Digital audio interface output •Digital peak meter
Digital Filter, DAC, Analog Low-Pass Filter Block •DBB (Digital Bass Boost)
•Supports double-speed playback •Digital de-emphasis
•Digital attenuation function •Zero detection function
•8fs oversampling digital filter
•S/N ratio: 100dB or more (master clock: 384fs typ.)Logical value: 109dB
•THD + N: 0.007% or less (master clock: 384fs typ.)•Rejection band attenuation: –60dB or more Applications CD players
Structure
Silicon gate CMOS IC
Absolute Maximum Ratings
•Supply voltage V DD
–0.3 to +7.0V •Input voltage V I –0.3 to +7.0V
(Vss – 0.3V to V DD + 0.3V)
•Output voltage V O –0.3 to +7.0V •Storage temperature Tstg –40 to +125°C •Supply voltage difference
V SS – AV SS –0.3 to +0.3V V DD – AV DD –0.3 to +0.3V
Note)AV DD includes XV DD , and AV SS includes XV SS .Recommended Operating Conditions •Su
pply voltage V DD 3.4 to 5.25V •Operating temperature Topr –20 to +75°C Note)The V DD (min.) for the CXD2519Q varies
according to the playback speed lection.
1When the internal operation of the CD-DSP side is t to double-speed mode and the crystal oscillation frequency is halved,normal-speed playback results.Input/Output Capacitances •Input pin C I 12 (max.)pF •Output pin C O 12 (max.)pF Note)Measurement conditions
V DD = V I = 0V f M = 1MHz
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Block Diagram
FSTT C4M RF ASYI ASYO ASYE BIAS XPCK FILO FILI PCO CLTV FOK SEIN CNIN D A T O
X L T O
C L K O
S E N S
D A T A
X L A T
C L O K
S P O A t o D
X L O N
S C O R
S B S O
E X C K
S Q S O
S Q C K作文我的心爱之物
M O N
M D P
人防系统
M D S
L O C K
X R O F
D O U T
L O U T 2
A I N 2
A O U T 2
L O U T 1
A I N 1诗图
A O U T 1
X T S L
V P C O 1
V P C O 2
V C K I
V 16M
V C T L
电商专员G T O P
X U G F
G F S
E M P H
W F C K
M N T 3
M N T 1
M N T 0
T E S 0
R F C K
C 2P O
W D C K
L R C K
P C M D
B C K
E M P H I
L R C K I
P C M D I
B C K I
S Y S M
RMUT LMUT
XTAI XTAO CKOUT
P W M I
V D D
V S S
L M U T
R M U T
T E S 2
C K O U T
S Q C K
S Q S O
S E N S
D A T A
X L A T
C L O K
S E I N
C N I N
D A T O
X L T O
C L K O
S P O A
S P O B
S P O C
S P O D
X L O N
F O K
V D D
V S S
M O N
M D P
M D S
L O C K
P W M I
cardenS Y S M
V D D
V S S
E X C K
S B S O
S C O R
W F C K
E M P H I
E M P H
D O U T
C 4M
F S T T
X T S L
M N T 0
M N T 1
M N T 3
X R O F
C 2P O
R F C K
G F S
X P C K
X U G F
G T O P
V D D
V S S
B C K I B C K
P C M D I
P C M D
L R C K I
LRCK WDCK ASYE ASYO ASYI BIAS RF AV DD CLTV AV SS FILI FILO PCO VCTL V16M VCKI VPCO1VPCO2TES1TES0
XV DD NC AV SS AV DD AOUT1AIN1LOUT1AV SS XTAI XTAO XV SS AV SS LOUT2AIN2AOUT2AV DD AV SS NC NC XRST
Pin No.Symbol I/O Description
Power supply (+5V).GND.
Left-channel zero detection flag.Right-channel zero detection flag.TEST output pin; normally open.
Master clock frequency-divider output. Selects and outputs XTAI ×1, × 1/2, × 1/4 or low only.
SQSO readout clock input.Sub Q 80-bit rial output.SENS output to CPU.Serial data input from CPU.
Latch input from CPU. Serial data is latched at the falling edge.Serial data transfer clock input from CPU.SENS input from SSP.Track jump count signal input.Serial data output to SSP.
Serial data latch output to SSP. Latched at the falling edge.Serial data transfer clock output to SSP.Microcomputer extended interface (input A).Microcomputer extended interface (input B).Microcomputer extended interface (input C).Microcomputer extended interface (input D).Microcomputer extended interface (output).
Focus OK input.
Ud for SENS output and the rvo auto quencer.Power supply (+5V).GND.
Spindle motor on/off control output.Spindle motor rvo control.Spindle motor rvo control.
GFS is sampled at 460Hz; when GFS is high, this pin outputs a high signal. If GFS is low eight concutive samples, this pin outputs low.Spindle motor external control input.TEST pin; normally GND.TEST pin; normally GND.
Wide-band EFM PLL charge pump output. Turned on/off by FCSW of address E.
——1, 01, 01, 01, 0
1, 01, 01, 01, 01, 01, 0——1, 01, Z, 01, Z, 01, 01, Z, 0——O O O O I O O I I I I I O O O I I I I O I ——O O O O I I I O
V DD V SS LMUT RMUT TES2CKOUT SQCK SQSO SENS DATA XLAT CLOK SEIN CNIN DATO XLTO CLKO SPOA SPOB SPOC SPOD XLON FOK V DD V SS MON MDP MDS LOCK PWMI TES0TES1VPCO2
123456789101112131415161718192021222324252627282930313233
Charge pump output for wide-band EFM PLL.VCO2 oscillation input for the wide-band EFM PLL.
VCO2 oscillation output for the wide-band EFM PLL.VCO2 control voltage input for the wide-band EFM PLL.
Master PLL charge pump output.
Master PLL (slave = digital PLL) filter output.
Master PLL filter input.
Analog GND.
Master VCO control voltage input.
Analog power supply (+5V).EFM signal input.
Constant current input of the asymmetry circuit.Asymmetry comparator voltage input.
EFM full-swing output (low = V SS , high = V DD ).Low: asymmetry circuit off; high: asymmetry circuit on
D/A interface. Word clock f = 2fs D/A interface. LR clock output f = fs LR clock input.
D/A interface. Serial data output (two’s complement, MSB first).D/A interface. Serial data input (two’s complement, MSB first).
D/A interface. Bit clock output.D/A interface. Bit clock input.
GND.
Power supply (+5V).GTOP output.XUGF output.XPLCK output.GFS output.RFCK output.C2PO output.XRAOF output.MNT3 output.MNT1 output.MNT0 output.
Crystal lector input. Low: 16.9344MHz; high: 33.8688MHz.
保护湿地
2/3 frequency-divider output for Pins 89 and 90.
1, Z, 0
1, 01, Z, 0Analog —
—
1, 0
1, 01, 0
1, 0
1, 0
——1, 01, 01, 01, 01, 01, 01, 01, 01, 01, 0
1, 0
O I O I O O I —I —I I I O I O O I O I O I ——O O O O O O O O O O I O
VPCO1VCKI V16M VCTL PCO FILO FILI AV SS CLTV AV DD RF BIAS ASYI ASYO ASYE WDCK LRCK LRCKI PCMD PCMDI BCK BCKI V SS V DD GTOP XUGF XPCK GFS RFCK C2PO XROF MNT3MNT1MNT0XTSL FSTT
343536373839404142434445464748495051525354555657585960616263646566676869
Pin No.Symbol I/O Description
4.2336MHz output. 1/4 frequency-divided VCKI output in CAV-W mode.Digital Out output.
Outputs a high signal when the playback disc has emphasis, and a low signal when there is no emphasis.
Inputs a high signal when de-emphasis is on, and a low signal when de-emphasis is off.
WFCK output.
Outputs a high signal when either subcode sync S0 or S1 is detected.Sub P to W rial output.SBSO readout clock input.
菠萝炒肉GND.
Power supply (+5V).
Mute input. Active when high.
Analog GND.
Analog power supply (+5V).Left-channel analog output.
Left-channel operational amplifier input.Left-channel LINE output.
Analog GND.
Power supply for master clock.
Crystal oscillation circuit input. Input the external master clock via this pin.Crystal oscillation circuit output.GND for master clock.
Analog GND.
Right-channel LINE output.
Right-channel operational amplifier input.Right-channel analog output.
Analog power supply (+5V).Analog GND.
System ret. Ret when low.
1, 01, 01, 0
1, 01, 01, 0
——
——
————
O O O I O O O I ——I
——O I O —I O —O I O ——I C4M DOUT EMPH EMPHI WFCK SCOR SBSO EXCK V SS V DD SYSM NC AV SS AV DD AOUT1AIN1LOUT1AV SS XV DD XTAI XTAO XV SS AV SS LOUT2AIN2AOUT2AV DD AV SS NC NC XRST
707172737475767778798081828384858687888990919293949596979899100
Notes)•PCMD is an MSB first, two’s complement output.
•GTOP is ud to monitor the frame sync protection status. (High: sync protection window relead.)•XUGF is the negative pul for the frame sync derived from the EFM signal. It is the signal before sync protection.
游记400字
•XPLCK is the inver of the EFM PLL clock. The PLL is designed so that the falling edge of XPLCK and the EFM signal transition point coincide.
•GFS goes high when the frame sync and the inrtion protection timing match.
•RFCK is derived with the crystal accuracy. This signal has a cycle of 136µs (during normal-speed).•C2PO reprents the data error status.
•XRAOF is generated when the 16K RAM exceeds the ±4F jitter margin.
Pin No.Symbol I/O Description
