Dynamic ODT
In certain application cas, and to further enhance signal integrity on the data bus, it is
desirable that the termination strength of the DDR3 SDRAM can be changed without
xinguissuing an MRS command, esntially changing the ODT termination on the fly. With
dynamic ODT R TT(WR)) enabled, the DRAM switches from nominal ODT R TT,nom) to dy-leighton
namic ODT R TT(WR)) when beginning a WRITE burst and subquently switches back to
nominal ODT R TT,nom) at the completion of the WRITE burst. This requirement is sup-
ported by the dynamic ODT feature, as described below.
Dynamic ODT Special U Ca
When DDR3 devices are architect as a single rank memory array, dynamic ODT offers a
special u ca: the ODT ball can be wired high (via a current limiting resistor prefer-
red) by having R TT,nom disabled via MR1 and R TT(WR) enabled via MR2. This will allow
the ODT signal not to have to be routed yet the DRAM can provide ODT coverage dur-
ing write access.
perphoneWhen enabling this special u ca, some standard ODT spec conditions may be viola-
ted: ODT is sometimes suppo to be held low. Such ODT spec violation (ODT not
新视野大学英语2读写教程答案LOW) is allowed under this special u ca. Most notably, if Write Leveling is ud, this
would appear to be a problem since R TT(WR) can not be ud (should be disabled) and
R TT(NOM) should be ud. For Write leveling during this special u ca, with the DLL
locked, then R TT(NOM) maybe enabled when entering Write Leveling mode and disabled
when exiting Write Leveling mode. More so, R TT(NOM) must be enabled when enabling
richard harmonWrite Leveling, via same MR1 load, and disabled when disabling Write Leveling, via
same MR1 load if R TT(NOM) is to be ud.
ODT will turn-on within a delay of ODTLon + t AON + t MOD + 1CK (enabling via MR1)
or turn-off within a delay of ODTLoff + t AOF + t MOD + 1CK. As en in the table below,
between the Load Mode of MR1 and the previously specified delay, the value of ODT is
uncertain. this means the DQ ODT termination could turn-on and then turn-off again
during the period of stated uncertainty.
Table 85: Write Leveling with Dynamic ODT Special Ca
Functional Description
The dynamic ODT mode is enabled if either MR2[9] or MR2[10] is t to 1. Dynamic
ODT is not supported during DLL disable mode so R TT(WR) must be disabled. The dy-
namic ODT function is described below:
•Two R TT values are available—R TT,nom and R TT(WR).
–The value for R TT,nom is prelected via MR1[9, 6, 2].
–The value for R TT(WR) is prelected via MR2[10, 9].
•During DRAM operation without READ or WRITE commands, the termination is con-
trolled.
–Nominal termination strength R TT,nom is ud.
–Termination on/off timing is controlled via the ODT ball and latencies ODTLon and
ODTLoff.
•When a WRITE command (WR, WRAP, WRS4, WRS8, WRAPS4, WRAPS8) is registered,
and if dynamic ODT is enabled, the ODT termination is controlled.
as one–A latency of ODTLcnw after the WRITE command: termination strength R TT,nom
bounded
switches to R TT(WR)
–A latency of ODTLcwn8 (for BL8, fixed or OTF) or ODTLcwn4 (for BC4, fixed or OTF)
after the WRITE command: termination strength R TT(WR) switches back to R TT,nom.
–On/off termination timing is controlled via the ODT ball and determined by ODT-
Lon, ODTLoff, ODTH4, and ODTH8.
–During the t ADC transition window, the value of R TT is undefined.
ODT is constrained during writes and when dynamic ODT is enabled (e Table 86
(page 197)). ODT timings listed in Table 84 (page 195) also apply to dynamic ODT
mode.
Table 86: Dynamic ODT Specific Parameters
Table 87: Mode Registers for R TT,nom
Note: 1.RZQ = 240Ω. If R TT,nom is ud during WRITEs, only RZQ/2, RZQ/4, RZQ/6 are allowed.
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以深圳市美光存储技术有限公司提供的参数为例，以下为MT41J128M16JT-125_K的详细参数，仅供参考
CK CK#DQS, DQS#
Address
Command
DQ
ODT
R TT
Notes:
1.Via MRS or OTF . AL = 0, CWL = 5. R TT,nom and R TT(WR) are enabled.
2.ODTH4 is defined from ODT registered HIGH to ODT registered LOW, so in this example,
ODTH4 is satisfied. ODT registered LOW at T5 is also legal.
Figure 112: Dynamic ODT: ODT Pin Asrted with WRITE Command for 4 Clock Cycles, BC4
CK CK#DQS, DQS#
Address
Command
Don’t Care
Transitioning DQ
account for
R TT
ODT
Notes:
1.Via MRS or OTF . AL = 0, CWL = 5. R TT,nom can be either enabled or disabled. If disabled,
ODT can remain HIGH. R TT(WR) is enabled.2.In this example ODTH4 = 4 is satisfied exactly.
Asynchronous ODT Mode
Asynchronous ODT mode is available when the DRAM runs in DLL on mode and when
either R TT,nom or R TT(WR) is enabled; however, the DLL is temporarily turned off in pre-
感恩节英文charged power-down standby (via MR0[12]). Additionally, ODT operates asynchronous-
ly when the DLL is synchronizing after being ret. See Power-Down Mode (page 184)
for definition and guidance over power-down details.
In asynchronous ODT timing mode, the internal ODT command is not delayed by AL
relative to the external ODT command. In asynchronous ODT mode, ODT controls R TT
by analog time. The timing parameters t AONPD and t AOFPD replace ODTLon/t AON
and ODTLoff/t AOF, respectively, when ODT operates asynchronously.
The minimum R TT turn-on time (t AONPD [MIN]) is the point at which the device termi-
nation circuit leaves High-Z and ODT resistance begins to turn on. Maximum R TT turn-
on time (t AONPD [MAX]) is the point at which ODT resistance is fully on. t AONPD
should i give up(MIN) and t AONPD (MAX) are measured from ODT being sampled HIGH.
The minimum R TT turn-off time (t AOFPD [MIN]) is the point at which the device termi-
nation circuit starts to turn off ODT resistance. Maximum R TT turn-off time (t AOFPD
[MAX]) is the point at which ODT has reached High-Z. t AOFPD (MIN) and t AOFPD
(MAX) are measured from ODT being sampled LOW.
