Features Array•Multi Channel Half–duplex Transceiver with Approximately ±2.5 MHz Programmable Tuning Range
英语单词墙•High FSK Sensitivity: –106 dBm at 20 kBaud/–109.5 dBm at 2.4 kBaud (433.92 MHz)•High ASK Sensitivity: –112.5 dBm at 10 kBaud/–116.5 dBm at 2.4 kBaud (433.92 MHz)•Low Supply Current: 10.5 mA in RX and TX Mode (3 V/TX with 5 dBm)
•Data Rate: 1 to 20 kBaud Manchester FSK, 1 to 10 kBaud Manchester ASK
•ASK/FSK Receiver Us a Low–IF Architecture with High Selectivity, Blocking, and Low Intermodulation (Typical Blocking 55 dB at ±750 kHz/61 dB at ±1.5 MHz and
70 dB at ±10 MHz, System I1dBCP = –30 dBm/System IIP3 = –20 dBm)
•226 kHz IF Frequency with 30 dB Image Rejection and 170 kHz Usable IF Bandwidth (TBD)
•Transmitter Us Clod Loop Fractional–N Synthesizer for FSK Modulation with a High PLL Bandwidth and an Excellent Isolation between PLL/VCO and PA •Tolerances of XTAL Compensated by Fractional–N Synthesizer with 800 Hz RF Resolution
•Integrated RX/TX–Switch, Single–ended RF Input and Output
•RSSI (Received Signal Strength Indicator)
•Communication to Microcontroller with SPI Interface Working at Maximum 500 kBit/s •Configurable Self Polling and RX/TX Protocol Handling with FIFO–RAM Buffering of Received and Transmitted Data
• 5 Push Button Inputs and One Wake–up Input are Active in Power–down Mode •Integrated XTAL Capacitors
平面设计培训机构•PA Efficiency: up to 38% (433.92 MHz/10 dBm/3 V)
•Low In–band Sensitivity Change of Typically ±1.8 dB within ±58 kHz Center Frequency Change in the Complete Temperature and Supply Voltage Range (TBD)
•Supply Voltage Switch, Supply Voltage Regulator, Ret Generation, Clock/Interrupt Generation and Low Battery Indicator for Microcontroller
•Fully Integrated PLL with Low Pha Noi VCO, PLL Loop Filter and Full Support of Multi–channel Operation with Arbitrary Channel Distance Due to Fractional–N Synthesizer
•Sophisticated Threshold Control and Quasi–peak Detector Circuit in the Data Slicer •Power Management via Different Operation Modes
•315 MHz, 345 MHz, 433.92 MHz, 868.3 MHz and 915 MHz without External VCO and PLL Components
•Inductive Supply with Voltage Regulator if Battery is Empty (AUX Mode)
•Efficient XTO Start–up Circuit (> –1.5 kΩ Worst Ca Real Start–up Impedance)•Changing of Modulation Type ASK/FSK and Data Rate without Component Changes •Minimal External Circuitry Requirements for Complete System Solution •Adjustable Output Power: 0 to 10 dBm Adjusted and Stabilized with External Resistor •ESD Protection at all Pins (2 kV HBM, 200 V MM, TBD FCDM)
•Supply Voltage Range: 2.4 V to 3.6 V or 4.4 V to 6.6 V
•Temperature Range: –40°C to +85°C
•Small 7×7 mm QFN48 Package
24841A–RKE–02/05
ATA5423/25/28/29 [Preliminary]
Applications
•Consumer Industrial Segment
•Access Control Systems
•Remote Control Systems
•Alarm and Telemetry Systems
•Energy Metering
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•Home Automation
Benefits
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•Low System Cost Due to Very High System Integration Level
•Only One Crystal Needed in System
•Less Demanding Specification for the Microcontroller Due to Handling of Power–down Mode, Delivering of Clock, Ret, Low Battery Indication and Complete Handling of Receive/Transmit Protocol and Polling
•Single–ended Design with High Isolation of PLL/VCO from PA and the Power Supply Allows a Loop Antenna in the Remote Control Unit to Surround the Whole Application
3
4841A–RKE–02/05 ATA5423/25/28/29 [Preliminary]
1.General Description
The ATA5423/25/28/29 is a highly integrated UHF ASK/FSK multi–channel half–duplex trans-ceiver
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with low power consumption supplied in a small 7 x 7 mm QFN48 package. The receive part is built as a fully integrated low–IF receiver, whereas direct PLL modulation with the frac-tional–N synthesizer is ud for FSK transmission and switching of the power amplifier for ASK transmission.
The device supports data rates of 1 kBaud to 20 kBaud (FSK) and 1 kBaud to 10 kBaud (ASK) in Manchester, Bi–pha and other codes in transparent mode. The ATA5428 can be ud in the 431.5 MHz to 436.5 MHz and in the 862 MHz to 872 MHz bands, the ATA5423 in the 312.5 MHz to 317.5 MHz band, the ATA5425 in the 342.5 MHz to 347.5 MHz band and the ATA5429 in the 912.5 MHz to 917.5 MHz band. The very high system integration level results in a small number of external components needed.
Due to its blocking and lectivity performance, together with the additional 15 dB to 20 dB loss and the narrow bandwidth of a typical loop antenna in a remote control unit, a bulky blocking SAW is not needed in the remote control unit. Additionally, the building blocks needed for a typi-cal remote control and access control system on both sides (the ba and the mobile stations) are fully integrated.
Its digital control logic with lf–polling and protocol generation enables a fast challenge–respon s
ystem without using a high–performance microcontroller. Therefore, the ATA5423/ATA5425/ATA5428/ATA5429 contains a FIFO buffer RAM and can compo and receive the physical messages themlves. This provides more time for the microcontroller to carry out other functions such as calculating crypto algorithms, composing the logical messages, and controlling other devices. Therefore, a standard 4–/8–bit microcontroller without special periphery and clocked with the CLK output of about 4.5 MHz is sufficient to control the communi-cation link. This is especially valid for passive entry and access control systems, where within less than 100 ms veral challenge–respon communications with arbitration of the communi-cation partner have to be handled.
It is hence possible to design bi–directional remote control and access control systems with a fast challenge–respon crypto function, with the same PCB board size and with the same cur-rent consumption as uni–directional remote control systems.
telecomFigure 1-1.System Block Diagram日语翻译工具
长沙培训班44841A–RKE–02/05ATA5423/25/28/29 [Preliminary]
Figure 1-2.Pinning QFN48 Table 1-1.Pin Description
Pin Symbol Function
1NC Not connected
2NC Not connected
3NC Not connected
4RF_IN RF input
5NC Not connected
6433_N868Selects RF input/output frequency range
7NC Not connected
8R_PWR Resistor to adjust output power
9PWR_H Pin to lect output power
10RF_OUT RF output
11NC Not connected
12NC Not connected
13NC Not connected
14NC Not connected
15NC Not connected
16AVCC Blocking of the analog voltage supply
17VS2Power supply input for voltage range 4.4 V to 6.6 V
18VS1Power supply input for voltage range 2.4 V to 3.6 V
19VAUX Auxiliary supply voltage input
20TEST1Test input, at GND during operation
21DVCC Blocking of the digital voltage supply
5
4841A–RKE–02/05 ATA5423/25/28/29 [Preliminary] 22
VSOUT Output voltage power supply for external devices 23
TEST2Test input, at GND during operation 24
XTAL1Reference crystal 25
XTAL2Reference crystal 26
NC Not connected 27
VSINT Microcontroller interface supply voltage 28
N_RESET Output pin to ret a connected microcontroller 29
IRQ Interrupt request 30
CLK Clock output to connect a microcontroller 31
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SDO_TMDO Serial data out/transparent mode data out 32
SDI_TMDI Serial data in/transparent mode data in 33
SCK Serial clock 34
DEM_OUT Demodulator open drain output signal 35
CS Chip lect for rial interface 36
RSSI Output of the RSSI amplifier 37
CDEM Capacitor to adjust the lower cut –off frequency data filter 38
RX_TX2GND pin to decouple LNA in TX mode 39
RX_TX1Switch pin to decouple LNA in TX mode 40
PWR_ON Input to switch on the system (active high)41
T5Key input 5 (can also be ud to switch on the system (active low))42
T4Key input 4 (can also be ud to switch on the system (active low))43
T3Key input 3 (can also be ud to switch on the system (active low))44
T2Key input 2 (can also be ud to switch on the system (active low))45
T1Key input 1 (can also be ud to switch on the system (active low))46
RX_ACTIVE Indicates RX operation mode 47
NC Not connected 48NC
Not connected GND Ground/backplane
Table 1-1.
Pin Description (Continued)Pin
Symbol Function
feist64841A–RKE–02/05ATA5423/25/28/29 [Preliminary]
Figure 1-3.Block Diagram
