Reduced Gigabit Media Independent Interface
(RGMII)
12/10/2000
optVersion 1.3
Reduced Pin-count Interface
For
manpower
Gigabit Ethernet Physical Layer Devices
Revision Level Date Revision Description
1.0 June 1, 2000 Relead for public review and comment
1.1 August 1, 2000 a) Modified RXERR and TXERR coding to reduce transitions and power
in normal conditions.
b) Removed CRS_COL pin and incorporated coding alternative for half
duplex implementation.
c) Found and corrected some inconsistencies in which clock was specified
for timing. PHY generated signals are bad on RXC and MAC
generated signals are bad on TXC. Specified that RXC is derived
from TXC to eliminate need for FIFOs in the MAC.
d) Modified timing diagram to incorporate PC board load conditions.
e) Removed references to SMII due to broad concerns about IP exclusivity
and added specification for 10/100 MII operation.
f) Modified Intellectual Property statement to address incorporation of IP
from multiple sources.
g) Modified document formatting.
1.2 Sept 11, 2000 a) Changed TD[4]/TXEN_TXERR signal name to TX_CTL
b) Changed RD[4]/RXEN_RXERR signal name to RX_CTL
c) Removed 100ps jitter requirement from TXC
d) Changed RXC derivation to received data stream
犀牛的英文e) Clarified Table 1 description of TX_CTL and RX_CTL logicalbates
functions
f) Required CRS asrtion/deasrtion to be synchronous for all speeds.
g) Returned timing numbers to absolute from percentages.
h) Relaxed 10/100 Duty cycle requirements to 40/60
i) Added verbage to allow clock cycle stretching during speed changes
and receive data and clock acquistion.
j) Modified Table 4 to incorporate optional in-band signaling of link
status, speed, and duplex.
k) Slight wording change on IP statements to limit scope and indemnify.
1.2a Sept 22, 2000 a) Clarified 3.4.2 statement to eliminate suggestion that in-band status was
初中英语学习策略only required for half-duplex.
b) Modified Table 2 to from "Clock to Data skew" to "Data to Clock
skew" to clarify the fact that clock is delayed relative to data.
c) Modified ction 4.0 to clarify that MDIO/MDC are also operating at
2.5v CMOS levels.
1.3 Dec 10, 2000 a) Clarified RX_CTL and TX_CTL functionality by modifying Figure 4
and adding Figure 5 and Figure 6.
b) Modified Table 3 to include the value of FF as rerved when
TX_CTL=0,1.
c) Reduced TskewR in Table 2 to a value of 2.6ns maximum for Gigabit
operation and relaxed it in note #1 for 10/100 operation.
d) Put maximum delay in note #1 of Table 2 of 2ns to ensure minimum
tup time for subquent edges.
1.0 Purpo
The RGMII is intended to be an alternative to the IEEE802.3u MII, the IEEE802.3z GMII and the TBI. The principle objective is to reduce the number of pins required to interconnect the MAC and the PHY from a maximum of 28 pins (TBI) to 12 pins in a cost effective and technology independent manner. In order to accomplish this objective, the data paths and all associated control signals will be reduced and control signals will be multiplexed together and both edges of the clock will be ud. For Gigabit operation, the clocks will operate at 125MHz, and for 10/100 operation, the clocks will operate at 2.5MHz or 25MHz respectively.
2.0 System Diagram
RTBI / RGMII
TXC
TD0
TD1
TD2
忆苦思甜什么意思
TD3 TP+
TX_CTL TP-
RD0 RP+
RD1 RP-
RD2
RD3
SD+ (optional)
RX_CTL
RXC
MDIO
MDC
FIGURE 1 (System Diagram)
3.0 Signal Definitions
The RGMII will share four data path signals with the Reduced Ten Bit Interface (RTBI) and share control functionality with the fifth data signal. With the inclusion of the MDIO/MDC rial management signals, the RTBI will not require independent control signals like LK_REF, BYTE_EN, etc. Register assignment of SERDES control bits is left to the implementer.
Signal Name RTBI RGMII Description TXC MAC MAC The transmit reference clock will be 125Mhz, 25Mhz, or
2.5Mhz +- 50ppm depending on speed.
TD[3:0] PCS MAC In RTBI mode, contains bits 3:0 on Ç of TXC and bits
8:5 on È of TXC. In RGMII mode, bits 3:0 on Ç of
TXC, bits7:4 on È of TXC
TX_CTL PCS MAC In RTBI mode, contains the fifth bit on Ç of TXC and
tenth bit on È of TXC. In RGMII mode, TXEN on Ç of
TXC, and a logical derivative of TXEN and TXERR on
È of TXC as described in ction 3.4
RXC PHY PHY The continuous receive reference clock will be 125Mhz,
25Mhz, or 2.5Mhz +- 50ppm. and shall be derived from
the received data stream
RD[3:0] PHY PHY In RTBI mode, contains bits 3:0 on Ç of RXC and bits
8:5 on È of RXC. In RGMII mode, bits 3:0 on Ç of
英语四级分数分布RXC, bits7:4 on È of RXC
RX_CTL PHY PHY In RTBI mode, contains the fifth bit on Ç of RXC and
tenth bit on È of RXC. In RGMII mode, RXDV on Ç
of RXC, and a derivative of RXDV and RXERR on È
of RXC as described in ction 3.4
TABLE 1 (Signal Definitions)
3.1 Signal Logic Conventions
All signals shall be conveyed with positive logic except as specified differently. For descriptive purpos, a signal shall be at a logic "high" when it is at a valid voltage level greater than V OH_MIN , and logic "low" when it is at a valid voltage level less than V OL_MAX. 3.2 Multiplexing of Data and Control
Multiplexing of data and control information is done by taking advantage of both edges of the reference clocks and nding the lower 4 bits on the Ç edge and the upper 4 bits on the È edge. Control signals can be multiplexed into a single clock cycle using the same technique.
RXC(at Transmitter)
RXD[8:5][3:0] RXD[7:4][3:0]
RX_CTL
RXC(at Receiver)
3.3 Timing Specifics (Measured with the circuit shown in FIGURE 3 and a timing threshold voltage of 1.25v)
Timing for this interface will be such that the clock and data are generated simultaneously by the sou
rce of the signals and therefore skew between the clock and data is critical to proper operation. This approach is being ud to provide tighter control of skew. Timing values are defined in percentages of the nominal clock period so to make this table speed independent.
Symbol Parameter Min Typical Max Units
TskewT Data to Clock output Skew (at Transmitter) -500 0 500 ps TskewR Data to Clock input Skew (at Receiver) *note 1
1 2.6 ns
Tcyc
baikalClock Cycle Duration *note 2 7.2 8 8.8 ns Duty_G
Duty Cycle for Gigabit *note 3 45 50 55 % Duty_T
Duty Cycle for 10/100T *note 3 40 50 60 % Tr / Tf
Ri / Fall Time (20-80%) .75
ns note 1: This implies that PC board design will require clocks to be routed such that an additional trace delay of greater than 1.5ns and less than 2.0ns
will be added to the associated clock signal. For 10/100 the Max value is unspecified.
note 2: For 10Mbps and 100Mbps, Tcyc will scale to 400ns+-40ns and 40ns+-4ns respectively.
note 3: Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domain
as long as minimum duty cycle is not violated and stretching occurs for no more than three Tcyc of the lowest speed transitioned between.
TABLE 2
R
R
FIGURE 3
3.4 TXERR and RXERR Coding
To reduce power of this interface, TXERR and RXERR, will be encoded in a manner that minimizes transitions during normal network operation. This is done by the following encoding method. Note that the value of GMII_TX_ER and GMII_TX_EN are valid at the rising edge of the clock while TXERR is prented on the falling edge of the clock. RXERR coding behaves in the same way.
TXERR <= GMII_TX_ER (XOR) GMII_TX_EN
RXERR <= GMII_RX_ER (XOR) GMII_RX_DV
When receiving a valid frame with no errors, RXDV=true is generated as a logic high on the Ç edge of RXC and RXERR=fal is generated as a logic high the È edge of RXC. When no frame is being received, RXDV=fal is generated as a logic low on the Çedge of RXC and RXERR=fal is generated as a logic low on the È edge of RXC.
When receiving a valid frame with errors, RXDV=true is generated as logic high on the Ç edge of RXC and RXERR=true is generated as a logic low on the È edge of RXC.
TXERR is treated in a similar manner. During normal frame transmission, the signal stays at a logic high for both edges of TXC and during the period between frames where no errors are to be indicated, the signal stays low for both edges.
TX_CTL GMII_TX_EN GMII_TX_ER TXD[7:0] Description quest parameter 0,0 0 0 00 through FF Normal inter-frame TRANSMIT_COMPLETE
0,1 0 1 00 through 0E Rerved —
0,1 0 1 0F Carrier Extend EXTEND (eight bits)
0,1 0 1 10 through 1E Rerved —
prize是什么意思0,1 0 1 1F Carrier Extend Error EXTEND_ERROR (eight bits)
0,1 0 1 20 through F F Rerved —
1,1 1 0 00 through FF Normal data transmission ZERO, ONE (eight bits)
1,0 1 1 00 through FF Transmit error propagation No applicable parameter NOTE—Values in TXD[7:0] column are in hexadecimalcertain
TABLE 3 (Allowable Encoding of TXD, TXERR and TXEN)
