Technical Data Sheet Part Number: T-CS-ET-0019-100
Document Number: I-IPA01-0158-USR Rev 06
February 2008
Technical Data Sheet
Reduced Gigabit Media Independent Interface (RGMII)
Reduced Gigabit Media Independent Interface (RGMII)
©2002 Cadence Design Systems, Inc. All rights rerved
Proprietary Notice
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Neither the whole nor any part of the information contained in, or the product described in this document may be adapted or reproduced in any material form except with the prior written permission of the copyright owner.
The product described in this document is subject to continuous developments and improvements and is supplied "AS IS". All warranties implied or expresd including but not limited to implied warranties or merchantability, or fitness for purpo, are excluded. Cadence Design Foundry, Inc shall not be liable for any loss or damage arising from the u of any information in this document, or any error or omission in such information, or any incorrect u of the product. Cadence Design Foundry products are not authorized for u as critical components in life support devices or systems without the express written approval of an authorid officer of Cadence Design Foundry, Inc. As ud herein:
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1. Life support devices or systems are devices of systems that are (a) intended for surgical
implant into the body or (b) support or sustain life, and who failure to perform, when properly ud in accordance with instructions for u provided in the labelling, can be reasonably expected to result in a significant injury to the ur.
2. A critical component is any component of a life support device or system or system
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who failure to perform can reasonably be expected to cau the failure of the life support device or system, or to affect its safety or effectiveness.
Featuresred notice
•Reduced GMII interface to physical layer
•Capable of working at 1 Gb/s, 100 Mb/s and 10 Mb/s data rates
•Selectable RGMII or reduced ten bit interface (RTBI) output
•Comma code-groups realignment in RTBI mode
•Optional registered DDR transmit output signals
Description
The Reduced Gigabit Media Independent Interface (RGMII) module provides an RGMII interface to an existing Ethernet MAC design with a GMII or TBI interface, for example the Gigabit Ethernet MAC (GEM) available from Cadence Design Foundry. The RGMII interface has been designed in accordance with the standards and specifications agreed in the Hewlett Packard document Reduced Gigabit Media Independent Interface (RGMII) Specifications. The are available for download at the following URLs
/rnd/pdfs/RGMIIv1_3.pdf and
/rnd/pdfs/RGMIIv2_0_final_hp.pdf
The RGMII module significantly reduces pin counts between the MAC and the physical layer. In applications where a number of Ethernet MAC and PHY interfaces are necessary, savings of up to 50% of the pin count are possible. This pin reduction is achieved by multiplexing data and control signals on both edges of the reference clocks. There are two modes of operation, RGMII mode and RTBI mode, with the current mode being lected by the tbi input signal.
•In RGMII mode, the number of data pins has been reduced from 8 to 4 for both receive and transmit, with a saving of 8 pins in total. This requires the u of both
edges of the clock in order to maintain the bandwidth. In RTBI mode, the ten bit
receive and transmit code groups are each split into two parate 5 bit groups and driven across the four data pins and the control pin, saving 10 pins in total.
•In RGMII mode, gmii_tx_er and gmii_tx_en are multiplexed over the rgmii_tx_ctl signal for transmission into a single clock period. Similarly for receive, gmii_rx_er and gmii_rx_dv have been encoded and multiplexed together into rgmii_rx_ctl. This
saves another 2 pins.
•In RGMII mode, both gmii_col and gmii_crs from the PHY to the MAC can be decoded internally thus saving another 2 pins.
judas什么意思For 1 Gbit/s operation, clocks operate at 125 MHz. For 100 Mbit/s and 10 Mbit/s operation, clocks operate at 25 MHz and 2.5 MHz respectively.
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The RGMII standard specifies a source synchronous clock with the data. It relies on the clock having a longer path delay than the data so that the data is resampled using the same edge of the clock on which it was generated.
In version 1.3 of the RGMII specification a 1.5 to 2ns clock delay is achieved through a PCB trace delay, in version 2.0 there is the option of introducing the delay on-chip at the source. Devices which support the internal delay are referred to as RGMII-ID.
Whether to support RGMII-ID is an implementation choice. The Cadence IP supports both versions of the specification.
Signal Interfaces
System Interface
Signal Name I/O Description
rgmii_tx_clk I RGMII transmit clock from system clock controller.
This clock must also be sourced to the PHY.
rgmii_tx_clk_sig I rgmii_tx_clk clock ud as signal to control
multiplexer for rgmii_txd output data.
rgmii_tx_n_clk I RGMII transmit clock inverted.
rgmii_rx_clk I RGMII receive clock from the PHY.
rgmii_rx_n_clk I RGMII receive clock inverted.
rbc1_sig I rgmii_rx_clk timed signal indicating that rbc1 is active,
ud as signal to control TBI receive data alignment. n_rgmii_txret I Ret corresponding to rgmii_tx_clk. This signal
should be asrted low asynchronously, and
deasrted high synchronously with rgmii_tx_clk. n_rgmii_tx_n_ret I Ret corresponding to rgmii_tx_n_clk. This
signal should be asrted low asynchronously, and
deasrted high synchronously with
rgmii_tx_n_clk.
n_rgmii_rxret I Ret corresponding to rgmii_rx_clk. This signal
should be asrted low asynchronously, and
deasrted high synchronously with rgmii_rx_clk. n_rgmii_rx_n_ret I Ret corresponding to rgmii_rx_n_clk. This
signal should be asrted low asynchronously, and
deasrted high synchronously with
rgmii_rx_n_clk.
MAC GMII Interface
Signal Name I/O Description
deal是什么意思gmii_txd[7:0] I Transmit data signal generated by the MAC. This input must
be synchronous with rgmii_tx_clk.
gmii_tx_en I Transmit enable signal generated by the MAC. This input
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must be synchronous with rgmii_tx_clk.
gmii_tx_er I Transmit error signal generated by the MAC. This input must
be synchronous with rgmii_tx_clk.
gmii_rxd[7:0] O Receive data to the MAC. This output is generated
synchronous to rgmii_rx_clk. In RTBI mode this output is
driven low.
gmii_rx_dv O Receive data valid signal to the MAC to indicate that the
value on gmii_rxd[7:0] is valid. This output is generated
synchronous to rgmii_rx_clk. In RTBI mode this output is
driven low.
gmii_rx_er O Receive error signal to the MAC to indicate that a code error
has been detected at the PHY. This output is generated
synchronous to rgmii_rx_clk. In RTBI mode this output is
the king 2 heartdriven low.
gmii_col O Collision detect signal to the MAC to indicate the occurrence
of transmission and reception at the same time in half duplex
mode. This output is asrted asynchronously. In RTBI
mode and when gmii_duplex_in is asrted this output is
driven low.
gmii_crs O Carrier n indication to the MAC. This signal is asrted
whenever the medium is in non-idle state and when
gmii_tx_en is asrted. This output is asrted
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asynchronously. In RTBI mode this output is driven low.
MAC TBI Interface
Signal Name I/O Description
tbi_tx_group[9:0] I 10 bit code group for transmit path. This input must be
synchronous with rgmii_tx_clk.
tbi_rx_group[9:0] O 10 bit code group for receive path. This output is
generated synchronous to rgmii_rx_clk. In RGMII
mode this output is driven low.
PHY RGMII Interface
Signal Name I/O Description
rgmii_txd[3:0] O Transmit data signal to the PHY.
rgmii_tx_ctl O Transmit control signal to the PHY. In RTBI mode this is
ud for a fifth bit of data.
rgmii_rxd[3:0] I Receive data signal from the PHY.
rgmii_rx_ctl I Receive control signal from the PHY. In RTBI mode this is
ud for a fifth bit of data.
