High-density performance line Arm®-bad 32-bit MCU with 256 to 512KB Flash, USB, CAN, 11 timers, 3 ADCs, 13 communication interfaces
Datasheet − production data Features
•Core: Arm® 32-bit Cortex®-M3 CPU
–72 MHz maximum frequency, 1.25DMIPS/MHz
(Dhrystone 2.1) performance at 0 wait state
memory access
–Single-cycle multiplication and hardware
division
•Memories
–256 to 512 Kbytes of Flash memory
–up to 64 Kbytes of SRAM
–Flexible static memory controller with 4 Chip Select. Supports Compact Flash, SRAM,
PSRAM, NOR and NAND memories
–LCD parallel interface, 8080/6800 modes •Clock, ret and supply management – 2.0 to 3.6V application supply and I/Os
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–POR, PDR, and programmable voltage detector (PVD)
–4-to-16 MHz crystal oscillator
–Internal 8 MHz factory-trimmed RC
–Internal 40 kHz RC with calibration
–32 kHz oscillator for RTC with calibration •Low power
–Sleep, Stop and Standby modes
–V BAT supply for RTC and backup registers • 3 × 12-bit, 1 µs A/D converters (up to 21
channels)
–Conversion range: 0 to 3.6 V
–Triple-sample and hold capability
–Temperature nsor
• 2 × 12-bit D/A converters
•DMA: 12-channel DMA controller
–Supported peripherals: timers, ADCs, DAC, SDIO, I2Ss, SPIs, I2Cs and USARTs •Debug mode
–Serial wire debug (SWD) & JTAG interfaces
世博会美国馆–Cortex®-M3 Embedded Trace Macrocell™•Up to 112 fast I/O ports
–51/80/112 I/Os, all mappable on 16 external interrupt vectors and almost all 5V-tolerant •Up to 11 timers
–Up to four 16-bit timers, each with up to 4
IC/OC/PWM or pul counter and quadrature
(incremental) encoder input
– 2 × 16-bit motor control PWM timers with dead-time generation and emergency stop
– 2 × watchdog timers (Independent and Window)–SysTick timer: a 24-bit downcounter
– 2 × 16-bit basic timers to drive the DAC
•Up to 13 communication interfaces
–Up to 2 × I2C interfaces (SMBus/PMBus)
–Up to 5 USARTs (ISO 7816 interface, LIN, IrDA capability, modem control)
–Up to 3 SPIs (18 Mbit/s), 2 with I2S interface multiplexed
–CAN interface (2.0B Active)
–USB 2.0 full speed interface
–SDIO interface
pollution有复数吗•CRC calculation unit, 96-bit unique ID •ECOPACK® packages
Table 1.Device summary Reference Part number
STM32F103xC
STM32F103RC STM32F103VC
equipment是什么意思
STM32F103ZC
STM32F103xD
STM32F103RD STM32F103VD
STM32F103ZD
STM32F103xE
STM32F103RE STM32F103ZE
STM32F103VE
July 2018DS5792 Rev 13
Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE
DS5792 Rev 13
High-speed external clock generated from a crystal/ceramic resonator
The high-speed external (HSE) clock can be supplied with a 4 to 16 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are bad on
characterization results obtained with typical external components specified in Table 23. In the application, the resonator and the load capacitors have to be placed as clo as
possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy).
For C L1 and C L2, it is recommended to u high-quality external ceramic capacitors in the 5pF to 25pF range (typ.), designed for high-frequency applications, and lected to match the requirements of the crystal or resonator (e Figure 22). C L1 and C L2 are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the ries combination of C L1 and C L2. PCB and MCU pin capacitance must be included (10pF can be ud as a rough estimate of the combined pin and board capacitance) when sizing C L1 and C L2. Refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website .
1.R EXT value depends on the crystal characteristics.
Table 23. HSE 4-16 MHz oscillator characteristics (1)(2)
1.Resonator characteristics given by the crystal/ceramic resonator manufacturer.
2.Guaranteed by characterization results.
Symbol Parameter
Conditions
Min Typ Max Unit f OSC_IN Oscillator frequency -4816MHz R F Feedback resistor
wip--200-k Ω C
Recommended load capacitance versus equivalent rial
resistance of the crystal (R S )(3)3.The relatively low value of the RF resistor offers a good protection against issues resulting from u in a
humid environment, due to the induced leakage and the bias condition change. However, it is recommended to take this point into account if the MCU is ud in tough humidity conditions.R S = 30 Ω-30
-pF
i 2HSE driving current V DD = 3.3 V, V IN =V SS
with 30 pF load
--1mA g m
Oscillator transconductance
Startup 25--mA/V t SU(HSE)(4)4.t SU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz
oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer
Startup time
V DD is stabilized
-
2
-
mstotally
DS5792 Rev 13
Table 31. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings(1) Symbol Parameter Min Max Unit t w(NE)FSMC_NE low time5t HCLK – 1.55t HCLK + 2ns
t v(NOE_NE)FSMC_NEx low to FSMC_NOE low0.5 1.5ns
t w(NOE)FSMC_NOE low time5t HCLK – 1.55t HCLK + 1.5ns
t h(NE_NOE)FSMC_NOE high to FSMC_NE high hold time–1.5-ns
t v(A_NE)FSMC_NEx low to FSMC_A valid-0ns
t h(A_NOE)Address hold time after FSMC_NOE high0.1-ns
t v(BL_NE)FSMC_NEx low to FSMC_BL valid-0ns
t h(BL_NOE)FSMC_BL hold time after FSMC_NOE high0-ns
t su(Data_NE)Data to FSMC_NEx high tup time2t HCLK + 25-ns
t su(Data_NOE)Data to FSMC_NOEx high tup time2t HCLK + 25-ns
t h(Data_NOE)Data hold time after FSMC_NOE high0-ns
t h(Data_NE)Data hold time after FSMC_NEx high0-ns
t v(NADV_NE)FSMC_NEx low to FSMC_NADV low-5ns
t w(NADV)FSMC_NADV low time-t HCLK + 1.5ns 1.C L = 15 pF.
1.Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not ud.
DS5792 Rev 13
Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE
英语小报图片Table 32. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings(1)(2)
smart什么意思
Symbol Parameter Min Max Unit
t w(NE)FSMC_NE low time3t HCLK – 13t HCLK + 2ns
谷歌翻译发音
t v(NWE_NE)FSMC_NEx low to FSMC_NWE low t HCLK – 0.5t HCLK + 1.5ns
t w(NWE)FSMC_NWE low time t HCLK – 0.5t HCLK + 1.5ns
larvat h(NE_NWE)FSMC_NWE high to FSMC_NE high hold time t HCLK-ns
t v(A_NE)FSMC_NEx low to FSMC_A valid-7.5ns
t h(A_NWE)Address hold time after FSMC_NWE high t HCLK-ns
t v(BL_NE)FSMC_NEx low to FSMC_BL valid-0ns
t h(BL_NWE)FSMC_BL hold time after FSMC_NWE high t HCLK – 0.5-ns
t v(Data_NE)FSMC_NEx low to Data valid-t HCLK + 7ns
t h(Data_NWE)Data hold time after FSMC_NWE high t HCLK-ns
t v(NADV_NE)FSMC_NEx low to FSMC_NADV low- 5.5ns
t w(NADV)FSMC_NADV low time-t HCLK + 1.5ns
1.C L = 15 pF.
2.Guaranteed by characterization results.
DS5792 Rev 13
