TP2540N3中文资料

更新时间:2023-06-07 14:04:19 阅读: 评论:0

1
11/12/01
Supertex Inc. does not recommend the u of its products in life support applications and will not knowingly ll its products for u in such applications unless it receives an adequate "products liability workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to the Supertex website: For complete liability information on all Supertex products, refer to the most current databook or to the Legal/Disclaimer page on the Supertex website.
BV DSS  /R DS(ON)V GS(th)I
cauD(ON)BV DGS (max)(max)(min)TO-92TO-243AA*
Die †-350V 25Ω-2.4V -0.4A TP2535N3——-400V
25Ω
-2.4V
-0.4A
TP2540N3
TP2540N8
TP2540ND
* Same as SOT-89.  Product supplied on 2000 piece carrier tape reels.
MIL visual screening available.
Ordering Information
TP2535TP2540
Low Threshold
Package Options
Features
❏Low threshold — -2.4V max.❏High input  impedance
❏Low input capacitance — 125pF max.❏Fast switching speeds ❏Low on resistance
❏Free from condary breakdown ❏Low input and output leakage
❏Complementary N- and P-channel devices
Low Threshold DMOS Technology
The low threshold enhancement-mode (normally-off) transis-tors utilize a vertical DMOS structure and Supertex's well-proven silicon-gate manufacturing process. This combination produces devices with the power handling capabilities of bipolar transistors and with the high input impedance and positive temperature coefficient inherent in MOS devices. Characteristic of all MOS structures, the devices are free from thermal runaway and thermally-induced condary breakdown.
Supertex’s vertical DMOS FETs are ideally suited to a wide range of switching and amplifying applications where very low threshold voltage, high breakdown voltage, high input impedance, low input capacitance, and fast switching speeds are desired.
Order Number / Package
P-Channel Enhancement-Mode Vertical DMOS FETs
Applications
waltdisney❏Logic level interfaces – ideal for TTL and CMOS ❏Solid state relays ❏Battery operated systems ❏Photo voltaic drives ❏Analog switches
❏General purpo line drivers ❏Telecom switches
Absolute Maximum Ratings
Drain-to-Source Voltage BV DSS Drain-to-Gate Voltage BVsubstitute
DGS Gate-to-Source Voltage
± 20V
Operating and Storage Temperature -55°C to +150°C
Soldering Temperature*
300°C
* Distance of 1.6 mm from ca for 10 conds.
你好吗的英语Product marking for TO-243AA
Where ❋ = 2-week alpha date code
TP5D ❋
元器件交易网
2
Symbol Parameter
Min Typ
Max
Unit Conditions
undertakeBV DSS TP2540-400TP2535
-350V GS(th)Gate Threshold Voltage
-
1.0
-2.4V V GS  = V DS , I D  = -1mA ∆V GS(th)Change in V GS(th) with Temperature    4.8mV/°C V GS  = V DS , I D  = -1mA I GSS Gate Body Leakage出席英语
-100nA V GS  = ±20V, V DS  = 0V I DSS
Zero Gate Voltage Drain Current
-10µA V闲客
GS  = 0V, V DS  = Max Rating V GS  = 0V, V DS  = 0.8 Max Rating T A  = 125°C
I D(ON)ON-State Drain Current -0.2-0.3A
V GS  = -4.5V, V DS  = -25V -0.4
-1.1V GS  = -10V, V DS  = -25V R DS(ON)Static Drain-to-Source 2030Ω
V GS  = -4.5V, I D  = -100mA ON-State Resistance
19
25V GS  = -10V, I D  = -100mA ∆R DS(ON)Change in  R DS(ON) with Temperature 0.75
%/°C V GS  = -10V, I D  = -100mA G FS Forward Transconductance 100
175m
V DS  = -25V, I D  = -100mA C ISS Input Capacitance
60125C OSS Common Source Output Capacitance 2070pF
C RSS Rever Transfer Capacitance 10
25t d(ON)Turn-ON Delay Time 10t r Ri Time
10t d(OFF)Turn-OFF Delay Time 20t f Fall Time
13V SD Diode Forward Voltage Drop -1.8
V V GS  = 0V, I SD  = -100mA t rr
Rever Recovery Time
300
英文祝福语ns
V GS  = 0V, I SD  = -100mA
Notes:
1.All D.C. parameters 100% tested at 25°C unless otherwi stated. (Pul test: 300µs pul, 2% duty cycle.)
2.All A.C. parameters sample tested.
Thermal Characteristics女士祛痘
V V GS = 0V, I D  = -2mA -1.0
mA Electrical Characteristics (@ 25°C unless otherwi specified)
ns
V GS  = 0V, V DS  = -25V f = 1 MHz
V DD  = -25V I D  = -0.4A R GEN  = 25Ω
pelosiSwitching Waveforms and Test Circuit
Package I D  (continuous)*
I D  (puld)Power Dissipation θjc θja I DR *I DRM @ T A  = 25°C
°C/W °C/W TO-92-86mA -0.6A 0.74W 125170-86mA -0.6A TO-243AA
-125mA
-1.2A
1.6W †
15
78†
-125mA
-1.2A
* I D  (continuous) is limited by max rated T j .
Mounted on FR5 Board, 25mm x 25mm x 1.57mm. Signficant P D  increa possible on ceramic substrate.
Drain-to-Source Breakdown Voltage PULSE DD
INPUT
OUTPUT
0V
V DD
0V
-10V
3
4
1235 Bordeaux  Drive, Sunnyvale, CA 94089
TEL: (408) 744-0100 • FAX: (408) 222-4895
11/12/01
©2001 Supertex Inc. All rights rerved. Unauthorized u or reproduction prohibited.

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