儿童书法培训2 Integrated Circuit Manufacturing:
A Technology Resource
2 — IC MANUFACTURING TECHNOLOGIES
While the integrated circuit drives the packaging and asmbly, the
I C
manufacturing process, and associated methodologies, rves as an invaluable technology resource. I C manufacturing is made up of a “Front End” and a “Back End”. The “Front End” encompass the actual fabrication of the I C and is most often referred to as “Wafer Fab”. The “Back End” covers subquent packaging, asmbly, and testing of the I C. Many of the materials, the process, procedures, and equipments, particularly tho associated with the photolithography, have direct application to relevant packaging and asmbly needs.
Areas of application for the types of methodologies supporting current and future IC packaging and asmbly include:
Wafer bumping for TAB and flip chip,
Wafer Level Packaging (WLP) for Chip Scale Packages (CSP),
Interconnect Substrates for MCPs, and
Level 2 High Density Interconnects, HDI PWBs.
The I C photolithographic process and the above applications share the same basic technology for pattern transfer. The inherent advantages of much of the I C methodologies can best be assd by first reviewing the various process emphasizing some of the important “lessons learned” and condly (and perhaps more importantly) their significance and impact on yields and cost-effective manufacturing.bronchitis
2.1 — Overview of the IC Manufacturing Process [1–4]
An IC is fabricated in a wafer format. Multiple ICs are manufactured simultaneously on a single wafer. Today wafers are procesd in 6", 8" and 12" diameters (Fig- ure 2-1). When completed, a wafer can contain literally hundreds or thousands of ICs. Larger wafers produce more devices and since the cost to manufacture changes little with size, the cost per IC is less. This of cour assumes yields are maintained in the transition from smaller to larger wafers. The switch to the larger wafer, h
owever, is also costly, typically involving a rather significant investment in new process equipment capable of handling the larger size wafers. The current 12" wafer
Integrated Circuit Packaging, Asmbly and Interconnections
16 is projected to remain in place through the next decade. Most major miconductor hous, which in the U.S. include I ntel, Texas I nstruments and Freescale Semiconductor (formerly Motorola), are now processing 12" wafers. The 6" and 8" wafers are found in the foundries. Foundries are facilities that provide wafer
manufacturing rvices to “fab-less” ASIC design hous.
(Courtesy IBM Corp.)
Figure 2-1. A 300 mm (12") and 200 mm (8") Diameter Silicon Wafer日系眼妆教程
The I C, basically a multilayered structure (Figure 2-2), is fabricated in a
quential process. Controlled impurities that create the active transistors are first embedded in the silicon using process such as oxidation, ion implantation, and diffusion. This is followed by the deposition of conductor and dielectric materials that form a multilevel conductor network. The network literally interconnects the millions of embedded transistors that may be contained within a single I C. This multilevel conductor network terminates at metallized bond pads on the surface of the I C that allow for access to the outside world when the I C is asmbled into a package.
副词Each layer within the structure shown must be properly defined using a pattern-
transfer process wherein an image on a photomask is transferred onto the surface of a wafer. To complete an I C as many as 25 or more photomasks, each containing a different image, are required.
Becau of the many steps involved in the manufacture of the I C major problems ari resulting in the loss of functional devices. This adverly affects overall yield of devices and directly impacts ma
nufacturing costs. Devices are lost becau of defects and contamination introduced during manufacture.
The process currently in place have evolved over the years from a continuing
and dedicated effort directed towards one objective, that is, to eliminate or minimize generation of defects and contaminants at each and every step in the manufacturing process and thereby optimize yields.
Integrated Circuit Manufacturing: A Technology Resource17
(Courtesy PTI Seminars, Inc.)
Figure 2-2. Schematic Cross-Section of a Si Integrated Circuit Major sources of defects are particulates in the operating environment, the materials and process themlves, the equipment, and associated fixtures and tooling. I n addition, operator involvement during manufacture can be a further contributor to yield loss due to improper dress, procedural errors and mishandling of wafers.
Identification of the various sources of defects and their elimination has resulted in many changes. As I C feature sizes began to rapidly decrea and complexity incread, critical changes were needed. The included, most notably, Strict control of the manufacturing environment and operator protocols, and
Continuing development of “near defect-free” photolithographic process covering the photomask and the exposure/imaging/printing equipment and
tooling.
2.2 — The Manufacturing Environment [5–6]
With decreasing feature size it became obvious that “particulates” contained in normal room air, whe
n inadvertently deposited on the wafer could create a defect that would result in loss of one or many ICs. A “cleanroom” operating environment to control the particulates in the air was esntial. The level of control required changed with each generation of IC. The level of cleanlines, and degree of controls are dictated by the particular process and device requirement, e.g., minimum feature size. Table 2-1 lists levels of cleanliness for cleanrooms and defines particle sizes and limits. The lower the classification number the higher level of control both as to the size and the number to be found in a given volume of air.
众议员 英文Integrated Circuit Packaging, Asmbly and Interconnections
18
Table 2-1. Cleanroom Classifications [US FED STD 209E Cleanroom Standards]
Maximum Number of Allowable Particle of Indicated Size per ft3
Class 0.1 µm 0.2 µm 0.3 µm 0.5 µm 1 µm 5 µm
3
7
1 35
75
30 10
10 350
10
1
100
300
750
100
10 1,000 1,000
全职英语翻译
100
100 10,000 10,000
1,000
1,000
10,000
100,000 100,000
Other sources of contaminants to be controlled include process chemicals, bacteria from process water, metallic ions found in process chemicals. and operator
and equipment related static discharge. High purity, high resistivity (18 megohms) deionized water (treated to remove metallic ions) is ud extensively during I C manufacturing supporting the many rinsing and cleaning operations. Special plumbing and the u of filters insure removal of damaging particles. I n addition, harmful bacterial contamination is removed by an ozone or ultraviolet light exposure treatment. Process chemicals are similarly subjected to much the same types of treatments and controls.
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Control of the room temperature (T) and relative humidity (RH) is also an esntial part of any cleanroom operating environment. Lack of control of T and RH
can adverly effect both materials and equipment and contribute to critical process irregularities. This is of particular significance in the photolithographics area where materials like photonsitive resists and associated process are affected. And, becau resist materials are nsitive to ultraviolet (uv) light, all photolithographic process are performed in a room with special lighting (yellow lighting) that eliminates unintentional but damaging exposures.
备忘录格式The “Back End” cleanroom requirements however, are quite different. Levels of control are orders of magnitude greater for “Front End” than “Back End”. “Backcia是什么意思
End” processing is usually maintained in a Class 1000 and higher operating environment. Early cleanrooms were Class 100. Today IC wafer fab is performed in
Class 1 cleanrooms. And, to further enhance the level of cleanliness, special process, e.g. the photolithographic process, are performed in parate enclosures
within the cleanroom (Figure 2-3).
2.2.1 — Operator Protocols
Strict operator protocols were also instituted and incorporated including,
Special training covering proper handling and storage of wafer,
The wearing of special cleanroom garments, and
Well-defined cleanroom operating procedures.
small什么意思
Integrated Circuit Manufacturing: A Technology Resource19
(Courtesy National Semiconductor)
Figure 2-3. A Class 1 Cluster Cell within a Class 10 Cleanroom
(Courtesy IBM Corp.)
Figure 2-4. Robotic Wafer Handling
n Wafer Fab operators are required to wear gowns worn specifically to eliminate particulates that could be introduced by the operator and the operator’s personal clothing.
U of “robotics” (Figure 2-4) as well as other automated wafer handling equipment and fixturing are implemented to minimize, wherever possible, operator intervention and potential operator induced damage resulting from mishandling and electrostatic discharge.
