design features 2-Channel and 4-Channel Pin-Selectable I2C Multiplexer Features High Noi Margin, Capacitance Buffering, Level Translation and Stuck Bus Recovery
石家庄出国留学中介Rajesh Venugopal
The first problem with large systems is that devices with hard-wired I2C address require address expansion to prevent conflicts. Second, noi caus glitches that can be interpreted as legitimate clock or data transitions, compromising data reli-ability. Third, I2C devices can cau the bus to stick low. Finally, timing specifications are increasingly difficult to meet, and clock frequencies are limited by the equivalent bus capacitance, which increas with system size and complexity. The LTC4312 and LTC4314 pin-lectable 2-channel
and 4-channel I2C multiplexers with bus buffers address the issues with a num-
ber of powerful features (e Table 1).
Since the two devices share the same
well donefeatures, except for the number of chan-
nels, this article focus on the LTC4314.
An upstream I2C bus (SDAIN, SCLIN) can be
connected to any combination of down-
stream bus through the LTC4314’s bus
buffers and multiplexer switches by driv-
ing the ENABLE pins of the desired output
bus high. Multiple devices having the
same address can be placed on different
bus and isolated using the ENABLE pins,
thereby achieving address expansion.
The buffers provide capacitance isola-
tion between the upstream bus and the
downstream bus, allowing for parti-
tioning of the bus capacitance. In single
supply systems, the buffers regulate the
bus up to 0.33 • V CC, providing a large
logic low noi margin. Ri time accel-
erators (RTA s) of appropriate strength
can be activated to overcome bus capaci-
tance limitations, reduce ri time and
allow for higher switching frequencies
even when operating with heavy loads.
The LTC4314 is compatible with the
throw
I2C standard and Fast Mode, SMBus and
PMBus specifications. Stuck bus recovery
circuitry disconnects the upstream bus
from downstream bus when SDA and
SCL have not been simultaneously high at
least once in 45ms, freeing the upstream
bus to resume communications. The recov-
ery circuitry also attempts to convince
The inherent simplicity of I2C and SMBus 2-wire protocols has made them a popular choice for communicating vital information in large systems. Both standards employ simple open-drain pull-down drivers with resistive or current source pull-ups. Nevertheless, veral practical problems ari as systems grow in complexity.
Table 1. Key features of the LTC4312 and LTC4314
the SCLIN voltage is < 0.33 • V MIN , and releas high when the SCLIN voltage
is > 0.33 • V MIN . The low offt makes the SCLOUT 1 waveform almost identical to the SCLIN waveform for voltages < 0.33 • V MIN . No output glitches occur as the input cross the V IL level of 0.33 • V MIN , as en in the SCLOUT 1 waveform.
package dat
A s the buffers are disconnected when both input and output bus voltage are > 0.33 • V MIN , any noi applied to the logic high state on one side is not propagated to the other side as long as that bus voltage does not drop below 0.33 • V MIN . This is en in Figure 1 where the logic high state of SCLOUT 1 is unaffected by noi on SCLIN.
Designers who are in control of the entire I 2C system can t the LTC4314 to operate at frequencies of up to 1MH z by adjusting the RC load on the bus and using strong RTA s (e Table 2). The LTC4314’s high-to-low propagation delay t PDHL is always positive , on the order of 100ns. Depending on bus loading conditions on the upstream and downstream sides of the LTC4314, the low-to-high propagation delay t PDLH of the LTC4314 can be either positive or negative. For systems operating at high frequen-cies (>400k H z ) designers should quantify the t PDLH -t PDHL skew in their SDA and SCL pathways and ensure data t-up and hold times are acceptable on all bus.
the high bandwidth buffers do not limit the ri rate of the bus , permitting them to stay on to a higher bus voltage. A s en in Figure 1, when a noisy 400k H z square wave signal is applied to SCLIN , the SCLOUT 1 waveform tracks SCLIN when
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the stuck device to relea high by gen-erating up to 16 clock puls and a stop bit on the enabled downstream bus. Finally , cards can be hot-swapped into and out of the LTC4314’s I 2C output bus provided that the channel being hot-swapped has been disabled. The LTC4314’s operating voltage range is V CC from 2.9V to 5.5V , V CC2 from 2.25V to 5.5V and bus voltages from 2.25V to 5.5V. The LTC4314 can level translate down to 1.5V and 1.8V bus under certain conditions if RTA s are disabled on the low voltage bus.
HIGH BANDWIDTH BUFFERS
IMPROVE NOISE MARGIN AND SPEED WHILE MAINTAINING LOW OFFSET
High noi margin is obtained by leaving the LTC4314 buffers on until both the input and output bus voltages are > 0.33 • V MIN , where V MIN is the lower of the V CC and V CC2
voltages. This is possible becau
500ns/DIV
2V/DIV
2V/DIV
Figure 1. The LTC4314 transmitting a noisy 400kHz I 2C signal applied to SCLIN. The SCLOUT1 waveform tracks SCLIN when SCLIN is a logic low. During
logic highs, noi on SCLIN above 0.33 • V MIN is not propagated to SCLOUT.
Figure 2. The LTC4314 in a nested addressing and level shifting application where a device on the upstream 3.3V bus communicates with devices on the 2.5V and 5V downstream bus. Only bus 1 and 4 are shown for simplicity.
The LTC4314 is compatible with the I 2C standard and Fast Mode, SMBus and PMBus specifications. Stuck bus recovery circuitry disconnects the upstream bus from downstream bus when SDA and SCL have not been simultaneously high at least once in 45ms, freeing the upstream bus to resume communications.
design features
PARALLELING LTC4314s TO ACHIEVE MULTIPLEXING OF MORE BUSES
Multiple LTC4314s can be connected in parallel to perform higher order multiplexing. Figure 4 shows a 1:8 multiplexer using two LTC4314s.
INTEROPERABILITY WITH NONCOMPLIANT I 2C DEVICES
The high buffer turn-off voltage of the LTC4314 ensures interoperability with noncompliant I 2C devices that drive a high V OL > 0.4V. This is shown in Figure 5 where a noncompliant device on channel 4 drives a high V OL = 0.6V. The buffer turn-off voltage is 1.089V , yielding a logic low noi margin
of > 0.4V at both the input and output.
RADIALLY CONNECTED TELECOMMUNICATIONS APPLICATION
Figure 3 shows the LTC4314 ud in a radially connected telecommunications application such as ATCA. Two shelf managers (SHMC s ) are ud to commu-nicate with slave I 2C devices for redun-dancy. Each shelf manager can have as many LTC4314s as required depending on the number of boards in the system and the desired radial /star configuration (6 × 4 in Figure 3). The ENABLE pins neocomimi
inside only one shelf manager are asrted high at any time. Since the LTC4314 can be cascaded with other Linear Technology bus buffers , up to 24 FRU s with Linear Technology bus buffers on their edges can be plugged into the backplane.
LEVEL TRANSLATION AND NESTED ADDRESSING
The circuit shown in Figure 2 illustrates level translation and nested addressing features of the LTC4314. The LTC4314 can level translate the input and output bus to voltages between 2.25V (1.5V and 1.8V under some circumstances) and 5.5V. In Figure 2 the LTC4314 translates a 3.3V input to 5V and 2.5V outputs. Only downstream bus 1 and 4 are shown for simplicity. Each output channel has a dedicated ENABLE pin lect that allows the master to communicate indepen-dently with slave devices with identical I 2C address provided that only one downstream bus is enabled at a time.
essaysFigure 3. The LTC4314 ud in a radially connected telecommunications system in a 6 × 4 arrangement. The ENABLE pins of only one shelf manager are high at any given time. Only the SDA pathway is shown for simplicity.
HOT SWAP™ APPLICATION
clipperI /O cards can be hot swapped into the downstream bus of an LTC4314 residing on a live backplane as shown in Figure 6. Before plugging or unplugging an I /O card , care must be taken to disable the corresponding output channel so that the card does not disturb any I 2C transaction that may be in progress. The connection to the inrted card must be enabled only when all ongoing transactions on the bus have completed and the bus is idle.
STUCK BUS DETECTION AND RECOVERY
Occasionally , slave devices get confud and get stuck in a low state. The LTC4314 monitors the enabled output bus to detect if clock and data have been simul-taneously high at least once in 45ms. If this condition is not detected , the LTC4314 asrts the FAULT flag low. If DISCEN is
generated , whichever comes first. After the final clock pul , a stop bit is generated to ret the bus for further communication. A rising edge on one or more ENABLE pins , after all ENABLE s have been taken low , is required to reestablish connection between the input and output. Doing this also clears the FAULT flag. The mas-ter can wait for the fault condition to clear (FAULT relead high), either on its own or through the 16 clock puls issued by the LTC4314, before toggling the LTC4314
’s ENABLE pins , or it can do so preemptively before the fault has cleared to reestablish connection. The master can then take appropriate action to clear the stuck low condition.
Figure 7 shows the waveforms dur-ing an SDAOUT 1 stuck low and recovery event. After the 45ms timeout period has elapd , the FAULT flag is asrted low and the input and output sides are discon-nected. This caus SDAIN to relea high.
tied high , the LTC4314 also disconnects the input and output sides and generates clock puls on the enabled downstream bus in an attempt to free the stuck bus. Clocking is stopped when data releas high or 16 clocks have been
Figure 4. Paralleling LTC4314 devices to realize a 1:8 multiplexer
noncompliant I 2= 0.6V
design features
0.33 • V MIN and to get 3m A of RTA cur-rent. The 3m A RTA current is enough to meet the 1µs sta
ndard mode I 2C ri time requirement (100k H z operation) for bus capacitances up to 690p F with DC bus pull-up currents < 4m A . Tie ACC high if no acceleration is needed. To lectively dis-able RTA s only on the outputs , ground V CC2 and either ground ACC or leave ACC open.
CONCLUSION
The LTC4314 and LTC4312 are pin-lect-able I 2C multiplexers that solve practi-cal design issues associated with large I 2C bus systems by providing capacitance buffering , nested addressing and level translation. The parts maintain a low offt and high logic low noi margin up to 0.33 • V CC . Their high bandwidth buffers and integrated RTA s allow for operation at frequencies up to 1MH z with guaranteed stability from zero to 1.2n F capacitive loads. They also discon-nect and recover bus when bus are stuck low and allow I /O cards to be hot swapped into and out of live systems. n
into the bus making them ri at a typi-cal rate of 40V /µs. The RTA current and the buffer turn-off voltage are lected by the ACC tting as shown in Table 2.For heavily capacitive bus with low to moderate noi , tie ACC low to meet system ri times and maximize SCL switch-ing frequency. Tying ACC low provides the strongest pull-up current over the maximum voltage range. For higher noi immunity , leave ACC open or tie it to 0.5 • V CC to t the buffer V IL to
Clock puls are generated on SCLOUT 1. SDAOUT 1 releas high before 16 clock puls have been generated. Clock puls-ing is stopped and a stop bit is gener-ated. When the ENABLE 1 pin is toggled , a connection is established between the input and output and a driven low level on SDAOUT 1 is propagated to SDAIN.If automatic stuck bus disconnec-tion is not desired , this feature can be disabled by tying DISCEN low. In this ca , during a stuck bus event , the FAULT flag is asrted low , but no stop bit or clock generation occurs and the input and output sides stay connected.
RISE TIME ACCELERATORS
The ri time accelerators (RTA s ) of the LTC4314 can be configured either in current source mode (ACC open), slew limited switch mode (ACC grounded), or disabled (ACC high). In the current source mode the RTA s source a constant 3m A current into the bus. In the slew controlled switch mode , the RTA s turn on in a controlled manner and source current
1ms/DIV
SCLOUT15V/DIV
5V/DIV 5V/DIV
ENABLE15V/DIV
CONNECT AT RISING EDGE OF ENABLE1DISCONNECT AT TIMEOUTcau的用法
STUCK LOW>45ms AUTOMATIC CLOCKING
DRIVEN LOW
RECOVERS
Figure 7. Bus waveforms during a SDAOUT1 stuck low and recovery event
Figure 6. The LTC4314 in a Hot Swap™ application where high when the other bus are idle.
Table 2. ACC control of the ri time accelerator current I RTA and buffer turn-off voltage V IL,RISING (typ)
