AD9361 Interface Specification
AD9361 Interface Specification ADI Confidential TABLE OF CONTENTS
Revision History (2)
General Description (3)
Parallel Digital Interface (4)
CMOS Mode Data Path and Clock Signals (4)
Maximum Clock Rates and Signal Bandwidths (5)
Single Port Half Duplex Mode (6)
Single Port Full Duplex Mode (9)
Dual Port Half Duplex Mode (12)
Dual Port Full Duplex Mode (Full Port) (14)
Data Bus Idle and Turnaround Periods (16)
Data Path Timing Parameters (16)
LVDS Mode Data Path and Clock Signals (17)
Data Path Signals (18)
Maximum Clock Rates and Signal Bandwidths (19)
Dual Port Full Duplex Mode (LVDS) (19)
Data Path Functional Timing (20)
Data Path Timing Parameters (22)
Adjustable Data Path Parameters (23)
钱英语怎么写
Configuration Control Register (23)
Serial Peripheral Interface (SPI) (26)
SPI Functional Layer (26)
SPI Data Transfer Protocol (26)
Timing Diagrams (28)
Additional Interface Signals (30)
CLOCK_OUT (30)
CTRL_IN[3:0] (30)
CTRL_OUT[7:0] (30)
EN_AGC (30)
GPO[3:0] (30)
RESETB (30)
SYNC_IN (30)
校长演讲REVISION HISTORY
11/2011 — Rev. 2.0
12/2011 — Rev. 2.1: Corrected wording to clarify explanations, added descriptions for two SPI register bits that were previously omitted. 4/2012 — Rev. 2.2: Corrected data path timing parameters, SPI timing to match the numbers listed in the latest datasheet.
6/2012 — Rev. 2.3: Corrected the description of using register 0x000 to tup the SPI bus, Updated the LVDS delay parameters for RX_FRAME and data relative to the DATA_CLK signal bad on statistical data.
7/2012 —Rev. 2.4: Corrected the LVDS timing parameter diagram in Figure 19 to show correct polarity for FB_CLK and show t HTX.
北京软件培训Text was added to Table 4 to clarify that tup and hold timing for TX data are relative to the FB_CLK falling edge.
1/2013 —Rev. 2.5: Corrected Figure 14 to remove any implied timing relationship between DATA_CLK and FB_CLK.
ADI Confidential AD9361 Interface Specification GENERAL DESCRIPTION
This document defines the parallel data ports and the Serial Peripheral Interface (SPI) that enable the transfer of data and control/status information between the AD9361 and a Ba Band Processor (BBP). Figure 1 illustrates the interfaces as well as a high-level view of how the AD9361 and BBP are ud in a broadband wireless system. The data interface operates in one of two modes: standard CMOS compatible mode or Low-voltage Differential Signal (LVDS) compatible mode. Each interface posss unique characteristics described in the following ction.
When CMOS mode is ud:
•Single ended CMOS logic compatibility is maintained.
•Either one or both data ports may be utilized. Using two ports allows for higher data throughput.
•Both Frequency-Division Duplex (FDD) and Time-Division Duplex (TDD) operation are supported with one data port or two.
When LVDS mode is ud:
•Data port signaling is differential LVDS, allowing up to 12-inch PCB traces/connector interconnects between the AD9361 and the BBP.
•Only the data port (including clocking and other associated timing signals) is LVDS compatible.
•Both FDD and TDD operation are supported.
Figure 1: AD9361 Interface
AD9361 Interface Specification ADI Confidential PARALLEL DIGITAL INTERFACE
The AD9361 digital interface is comprid of two parallel data ports and veral clock, synchronization, and control signals. The signals can be configured as single-ended CMOS signals or as LVDS signals for systems that require high speed, low noi data transfer. The following ctions explain the details of the signals that make up the digital interface and their properties when configured for each mode.
CMOS MODE DATA PATH AND CLOCK SIGNALS
This ction describes operation of the AD9361 data path in CMOS mode. In this mode, the AD9361 data path interface can u either or both parallel data ports to transfer data samples between the AD9361 and the BBP. The bus transfers are controlled using simple hardware handshake signaling. The two ports can be operated in either FDD mode or bidirectional TDD mode. In FDD mode, half of the bits transmit data and the other half receive data simultaneously. In TDD mode, the transmit data and receive data are alternately transferred between the AD9361 and the BPP on the same pins during different time slots. For applications that do not require fast effecti
ve data rates, a single port can be ud to minimize connections to the AD9361. The data path interface consists of the signals described in the following ctions.
P0_D[11:0] and P1_D[11:0]
Both Port 0 (P0) and Port 1 (P1) have a 12-bit parallel data bus (D[11:0]) that transfers data between the BBP and the AD9361. Each bus is identical to the other in size and function, so D[11:0] is ud in this document to refer to either P0 or P1. The bus can be configured as transmit-only, receive-only, or bi-directional.
DATA_CLK
The DATA_CLK signal is provided to the BBP as a master clock for the RX data path. In CMOS mode, it is generated internally and output on the DATA_CLK_P pin (DATA_CLK_N is left unconnected). The same clock is ud for P0, P1, or both ports depending on the data bus configuration. The BBP us this master clock as the timing reference for the interface data transfers and for the baband data processing. DATA_CLK provides source-synchronous timing with dual edge capture (DDR) or single rising-edge capture (SDR) data transfer during receive operation.
The DATA_CLK frequency generated depends on the system architecture (number of RF channels, degree of over-sampling and bandwidth mode, etc.).
FB_CLK
FB_CLK is a feedback (looped-back) version of DATA_CLK driven from the BBP to the FB_CLK_P pin in CMOS mode (FB_CLK_N is left unconnected). FB_CLK allows source-synchronous timing with rising edge capture for the burst control signals (TX_FRAME, ENABLE, and TXNRX). FB_CLK also provides source-synchronous timing with dual edge capture (DDR) or single rising-edge capture (SDR) for D[11:0] data signals during TX bursts (both P0 and P1). Note that FB_CLK must be a feedback version of DATA_CLK (exact same frequency and duty cycle), but there is no pha relationship requirement between the two clock signals.
RX_FRAME
RX_FRAME is driven by the AD9361 to identify valid data for the RX data path (both P0 and P1). A high transition indicates the beginning of the frame. RX_FRAME can be t to be a single high transition at the beginning of a burst and stay high throughout the burst, or it can be t to be a pul train that has a rising edge at the beginning of each frame (50% duty cycle). In CMOS mode, this si
gnal is output from the RX_FRAME_P pin (RX_FRAME_N can be left unconnected).
TX_FRAME
TX_FRAME is driven by the BBP to identify valid data for the TX data path (both P0 and P1). A high transition indicates the beginning of the frame. The BBP can t TX_FRAME to be a single high transition at the beginning of a burst that stays high throughout the burst, or it can t TX_FRAME to a pul train that has a rising edge at the beginning of each frame (50% duty cycle). The AD9361 accepts either format. In CMOS mode, this signal is input to the TX_FRAME_P pin (TX_FRAME_N is tied to ground).
The AD9361 transmits null data (all zeros) until the first TX_FRAME indicates valid data. This is a uful feature when the TX path completes a transmit operation in FDD independent mode and the data path is not automatically flushed. In this ca, the TX_FRAME pin can be held low to complete the data flushing operation. See the Enable State Machine (ENSM) Guide for more details.
Note that the interface requires both RX_FRAME and TX_FRAME signals to function properly.
ADI Confidential AD9361 Interface Specification
ENABLE
ENABLE is driven from the BBP to the AD9361 to provide data transfer burst control (along with TXNRX) in TDD mode. ENABLE is asrted by the BBP for a minimum of a single DATA_CLK cycle to indicate the start of each burst. It is subquently asrted a cond time for a minimum of a single DATA_CLK cycle to indicate the end of each burst.
The AD9361 internally tracks the quence of ENABLE puls to interpret each pul correctly as either the start or finish of each burst. The ENABLE signal also can be configured in level mode, in which an edge transition (not puls) determines when the ENSM moves between states. The level sampled on TXNRX during each ENABLE start event controls the bus direction in TDD mode. The start and finish latencies (between the ENABLE puls being sampled by the AD9361 and the prence of the first and last valid data samples on the bus) vary depending on data path configuration. The RX_FRAME and TX_FRAME signals are ud to determine valid data by the BBP and the AD9361, respectively. The FB_CLK signal is ud to sample this input.
In FDD mode, the ENABLE signal rves as the single control input to determine the state of the ENSM. There is also an alternative FDD mode in which the ENABLE signal can be redefined as RX
ON, a direct hardware control input to the ENSM that controls the RX function. In this mode (called FDD Independent Control Mode), the BBP independently controls the RX function, which can result in power consumption savings.
TXNRX
TXNRX is driven from the BBP to the AD9361 and provides data transfer burst control (along with ENABLE) when the data bus is in TDD mode. When ENABLE is sampled high by the AD9361 to start a burst, the level on TXNRX is also sampled to determine the data direction. In TDD mode, TXNRX sampled high indicates a transmit burst and TXNRX sampled low indicates a receive burst.
The TXNRX signal level must be maintained throughout a data transfer burst (a valid logic level). The TXNRX signal may be established any number of cycles (≥ 0) before the ENABLE start pul is sampled, and it may be changed any number of cycles (≥ 0) after the ENABLE finish pul is sampled. It is important to note that the TXNRX signal should only change state while the ENSM is in the ALERT state becau the TXNRX signal powers up and down the synthesizers directly in TDD mode.
In normal FDD mode, the TXNRX signal is ignored but must be held at a valid logic level. There is al
so an alternative FDD mode in which the TXNRX signal can be redefined as TXON, a direct hardware control input to the ENSM that controls the TX function. In this mode (called FDD Independent Control Mode), the BBP independently controls the TX function, which can result in power consumption savings.
MAXIMUM CLOCK RATES AND SIGNAL BANDWIDTHS
The data listed in Table 1 compares the maximum data clock rates and maximum RF signal bandwidths in the different allowable operating modes for the CMOS data bus configuration. Maximum RF bandwidths are listed for two cas: sampling using the minimum sample rate that avoids aliasing, and sampling using 2× oversampling. Details of each mode are given in subquent ctions. The maximum DATA_CLK rate is limited to 61.44 MHz, so the data rates are limited by this factor and the 56 MHz maximum analog filter bandwidth.
Table 1: Maximum Data Rates (SDR and DDR) and Signal Bandwidths
Operating Mode
1R1T Configurations 1R2T / 2R1T / 2R2T Configurationsquicktime是什么
vary
Maximum Datajjcc
Rate (Combined
I and Q Words)
Maximum RF Channel Signal Bandwidth Maximum Data Rate
(Combined I and Q
Words)
Maximum RF Channel Signal Bandwidth
(per channel)
Using Minimum
Sample Frequency
Using 2×
Oversampling
防火小知识Using Minimum
Sample Frequency
Using 2×
Oversampling SDR
(Msps)
DDR
(Msps)
SDR Bus
(MHz)
DDR Bus
(MHz)
SDR Bus
(MHz)
DDR Bus
(MHz)
dairySDR
(Msps)
DDR
(Msps)
SDR Bus
(MHz)
DDR Bus
(MHz)
SDR Bus
(MHz)
DDR Bus
(MHz)
Single
Port Half
Duplex
30.72 61.44 30.72 56 115.36 30.72 15.36 30.72 15.36 30.72 7.68 15.36
Single
Port Full
Duplex
15.36 30.72 15.36 30.72 7.68 15.36 7.68 15.36 7.68 15.36 3.84 7.68
Dual Port
grow是什么意思Half
Duplex
61.44 122.88 56 156 130.72 56 130.72 61.44 30.72 56 115.36 30.72
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Dual Port
Full
Duplex
30.72 61.44 30.72 56 115.36 30.72 15.36 30.72 15.36 30.72 7.68 15.36 1 Limited by the analog filter bandwidth
