Triple Differential Driver
With Output Pull-Down
AD8133 Rev.0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its u, nor for any
infringements of patents or other rights of third parties that may result from its u. Specifications subject to change without notice. No licen is granted by implication or otherwi under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329. Fax: 781.326.8703© 2004 Analog Devices, Inc. All rights rerved.
FEATURES
Triple high speed fully differential driver
une225 MHz −3 dB large signal bandwidth
Easily drives 1.4 V p-p video signal into source-terminated 100 Ω UTP cable
1600 V/µs slew rate
Fixed internal gain of 2
Internal common-mode feedback network
Output balance error −60 dB @ 50 MHz
Differential input and output
Differential-to-differential or single-ended-to-differential operation
reductionAdjustable output common-mode voltage
Output pull-down feature for line isolation
Low distortion: 64 dB SFDR @ 10 MHz on 5 V supply,
R L, dm = 200 Ω
Low offt: 4 mV typical output referred on 5 V supply
Low power: 26 mA @ 5 V for three drivers
Wide supply voltage range: +5 V to ±5 Vsdt
Available in space-saving packaging: 4 mm × 4 mm LFCSP
APPLICATIONS
KVM (keyboard-video-mou) networking
UTP (unshielded twisted pair) driving
Differential signal multiplexing
GENERAL DESCRIPTION
The AD8133 is a major advancement beyond using discrete op amps for driving differential RGB signals over twisted pair cable. The AD8133 is a triple, low cost differential or single-ended input to differential output driver, and each amplifier has a fixed gain of 2 to compensate for the attenuation o
ignore什么意思
f line ter-mination resistors. The AD8133 is specifically designed for RGB signals but can be ud for any type of analog signals or high speed data transmission. The AD8133 is capable of driving either Cate-gory 5 unshielded twisted pair (UTP) cable or differential printed circuit board transmission lines with minimal signal degradation. The outputs of the AD8133 can be t to a low voltage state to be ud with ries diodes for line isolation, allowing easy dif-ferential multiplexing over the same twisted pair cable. The AD8133 driver can be ud in conjunction with the AD8129 and AD8130 differential receivers.
FUNCTIONAL BLOCK DIAGRAM
OPD
V S–
–IN A
+IN A
V S–
V OCM C
V S+
–IN C
+IN C
beloved是什么意思V S–
–OUT A–OUT C
V
S
+
–
I
N
B
+
I
N
B
V
S
–
V
O
C
M
A
V
O
C
M
B
+
O
U
T
A
V
S
+
+
O
U
T
B
–
O
U
T
B
V东野圭吾推理系列04
S
+
+
O
U
T
C
乔布斯传下载4
7
6
9
-
-
1
Figure 1.
FREQUENCY (MHz)
O
U
T
P
U
T
B
A
L
A
N
C
E
E
R
R
O
R
(
d
B
)
–20
–10
–40
–30
–60
–50
–80
–70
–100
–90
4
7
6
9
-
-
3
4
Figure 2. Output Balance vs. Frequency Manufactured on Analog Devices’ next generation XFCB bipo-lar process, the AD8133 has a large signal bandwidth of
225 MHz and a slew rate of 1600 V/µs. The AD8133 has an internal common-mode feedback feature that provides output amplitude and pha matching that is balanced to −60 dB at
50 MHz, suppressing harmonics and minimizing radiated elec-tromagnetic interference (EMI).
The output common-mode level is easily adjustable by applying a voltage to the V OCM input pin. The V OCM input can also be ud to transmit signals on the output common-mode voltages. The AD8133 is available in a 24-lead LFCSP package and can operate over the temperature range of −40°C to +85°C.
AD8133
Rev. 0 | Page 2 of 16
TABLE OF CONTENTS
<3 Absolute 5 5 5 Pin Configuration and 6 Typical 7 Theory 12 Definition 12 Analyzing an 12 12 Calculating an Application Circuit’s .13 Input Common-Mode V oltage Range in Single-Supply
<13 Driving a 13 Output Pull-Down (OPD)........................................................13 Output 14 Driving RGB Video Signals Ove
文件箱r Category-5 14 15 15 Layout and Power Supply 15 15 Expod Paddle (EP)..................................................................15 16 Ordering Guide.. (16)
REVISION HISTORY
7/04—Revision 0: Initial Version
AD8133
去澳洲留学Rev. 0 | Page 3 of 16
SPECIFICATIONS
V S = ±5V , V OCM = 0 V @ 25°C, R L , dm = 200 Ω, unless otherwi noted. T MIN to T MAX = −40°C to +85°C. Table 1.
Parameter Conditions Min Typ Max Unit DIFFERENTIAL INPUT PERFORMANCE DYNAMIC PE
RFORMANCE −3 dB Small Signal Bandwidth V O = 0.2 V p-p 450 MHz −3 dB Large Signal Bandwidth V O = 2 V p-p 225 MHz Bandwidth for 0.1 dB Flatness V O = 0.2 V p-p 60 MHz V O = 2 V p-p 55 MHz Slew Rate V O = 2 V p-p, 25% to 75% 1600 V/µs Settling Time to 0.1% V O = 2 V Step 15 ns Isolation between Amplifiers f = 10 MHz, between Amplifiers A and B 81 dB DIFFERENTIAL INPUT CHARACTERISTICS Input Common-Mode Voltage Range −5 to +5 V Input Resistance Differential 1.5 kΩ Single-Ended Input 1.13 kΩ Input Capacitance Differential 1 pF DC CMRR ∆V OUT, dm /∆V IN, cm , ∆V IN, cm = ±1 V −50 dB DIFFERENTIAL OUTPUT CHARACTERISTICS Differential Signal Gain ∆V OUT, dm /∆V IN, dm ; ∆V IN, dm = ±1 V 1.925 1.960 2.000 V/V Output Voltage Swing Each Single-Ended Output V S− + 1.9 V S+ – 1.6 V Output Offt Voltage −24 +4 +24 mV Output Offt Drift T MIN to T MAX ±30 µV/°C Output Balance Error ∆V OUT, cm /∆V IN, dm , ∆V OUT, dm = 2 V p-p, f = 50 MHz −60 dB DC −70 −58 dB Output Voltage Noi (RTO) f = 1 MHz 25 nV/√Hz Output Short-Circuit Current 90 mA V OCM to V O, cm PERFORMANCE V OCM DYNAMIC PERFORMANCE −3 dB Bandwidth ∆V OCM = 100 mV p-p 330 MHz Slew Rate V OCM = −1 V to +1 V, 25% to 75% 1000 V/µs DC Gain ∆V OCM = ±1 V 0.980 0.995 1.005 V/V V OCM INPUT CHARACTERISTICS Input Voltage Range ±3.1 V Input Resistance 70 kΩ Input Offt Voltage −15 −6 +15 mV Input Offt Voltage Drift T MIN to T MAX ±50 µV/°C DC CMRR ∆V OUT, dm /∆V OCM , ∆V OCM = ±1 V −42
dB POWER SUPPLY Operating Range +4.5 ±6 V Quiescent Current 28 29 mA PSRR ∆V OUT, dm /∆V S ; ∆V S = ±1 V −84 −76 dB OUTPUT PULL-DOWN PERFORMANCE OPD Input Low Voltage V S− to V S+ − 4.15 V OPD Input High Voltage V S+ − 3.15 to V S+ V OPD Input Bias Current 67 90 µA OPD Asrt Time 100 ns OPD De-Asrt Time 100 ns Output Voltage When OPD Asrted Each Output, OPD Input @ V S + V S− + 0.86 V S− + 0.90 V
AD8133
Rev. 0 | Page 4 of 16
V S = 5 V , V OCM = 2.5 V @ 25°C, R L, dm = 200 Ω, unless otherwi noted. T MIN to T MAX = −40°C to +85°C. Table 2.department简写
Parameter Conditions Min Typ Max Unit DIFFERENTIAL INPUT PERFORMANCE DYNAMIC PERFORMANCE −3 dB Small Signal Bandwidth V O = 0.2 V p-p 400 MHz −3 dB Large Signal Bandwidth V O = 2 V p-p 200 MHz Bandwidth for 0.1 dB Flatness V O = 0.2 V p-p 50 MHz Slew Rate V O = 2 V p-p, 25% to 75% 1400 V/µs Settling Time to 0.1% V O = 2 V Step 14 ns Isolation Between Amplifiers f = 10 MHz, between Amplifiers A and B 75 dB DIFFERENTIAL INPUT CHARACTERISTICS Input Common-Mode Voltage Range 0 to 5 V Input Resistance Differential
1.5 kΩ Single-Ended Input 1.13 kΩ Input Capacitance Differential 1 pF DC CMRR ∆V OUT, dm /∆V IN, cm , ∆V IN, cm = ±1 V −50 dB DIFFERENTIAL OUTPUT CHARACTERISTICS Differential Signal Gain ∆V OUT, dm /∆V IN, dm ; ∆V IN, dm = ±1 V 1.925 1.960 2.000 Output Voltage Swing Each Single-Ended Output V S − + 1.25 V S+ − 1.15 V Output Offt Voltage −24 +4 +24 mV Output Offt Drift T MIN to T MAX ±30 µV/°C Output Balance Error ∆V OUT, cm /∆V IN, dm , ∆V OUT, dm = 2 V p-p, f = 50 MHz −60 dB DC −70 −58 dB Output Voltage Noi (RTO) f = 1 MHz 25 nV/√Hz Output Short-Circuit Current 90 mA V OCM PERFORMANCE V OCM DYNAMIC PERFORMANCE −3 dB Bandwidth ∆V OCM = 100 mV p-p 290 MHz Slew Rate V OCM = −1 V to +1 V, 25% to 75% 700 V/µs DC Gain ∆V OCM = ±1 V, T MIN to T MAX 0.980 0.995 1.005 V/V V OCM INPUT CHARACTERISTICS Input Voltage Range 1.25 to 3.85 V Input Resistance 70 kΩ Input Offt Voltage −15 +2 +15 mV Input Offt Voltage Drift T MIN to T MAX ±50 µV/°C DC CMRR ∆V O, dm /∆V OCM ; ∆V OCM = ±1 V −42 dB POWER SUPPLY Operating Range +4.5 ±6 V Quiescent Current 26 27 mA PSRR ∆V OUT, dm /∆V S ; ∆V S = ±1 V −84 −76 dB OUTPUT PULL-DOWN PERFORMANCE OPD Input Low Voltage V S− to V S+ − 3.85 V OPD Input High Voltage V S+ − 2.85 to V S+ V OPD Input Bias Current 63 80 µA OPD Asrt Time 100 ns OPD De-Asrt Time 100 ns Output Voltage When OPD Asrted Each Output, OPD Input @ V S + V S− + 0.79 V S− + 0.82 V
AD8133
Rev. 0 | Page 5 of 16
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Rating Supply Voltage 12 V All V OCM ±V S Power Dissipation See Figure 3 Input Common-Mode Voltage ±V S Storage Temperature −65°C to +125°C Operating Temperature Range −40°C to +85°C
Lead Temperature Range
(Soldering 10 c) 300°C Junction Temperature 150°C
Stress above tho listed under Absolute Maximum Ratings may cau permanent damage to the device. This is a stress rat-ing only and functional operation of the device at the or any other condi
tions above tho indicated in the operational c-tion of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-ca conditions, i.e., θJA is specified for the device soldered in a circuit board in still air. Table 4. Thermal Resistance with the Underside Pad Connected to the Plane
Package Type/PCB Type θJA Unit 24-Lead LFCSP/4-Layer 70 °C/W
Maximum Power Dissipation
The maximum safe power dissipation in the AD8133 package is limited by the associated ri in junction temperature (T J ) on the die. At approximately 150°C, which is the glass transition temperature, the plastic changes its properties. Even temporarily exceeding this temperature limit may change the stress that the package exerts on the die, permanently shifting the para-metric performance of the AD8133. Exceeding a junction tem-perature of 175°C for an extended period of time can result in changes in the silicon devices potentially causing failure. The power dissipated in the package (P D ) is the sum of the quiescent power dissipation and the power dissipated in the pa
ckage due to the load drive for all outputs. The quiescent power is the voltage between the supply pins (V S ) times the quiescent current (I S ). The load current consists of differential and common-mode currents flowing to the loads, as well as currents flowing through the internal differential and common-mode feedback loops. The internal resistor tap ud in the
common-mode feedback loop places a 4 kΩ differential load on the output. RMS output voltages should be considered when dealing with ac signals.
Airflow reduces θJA . Also, more metal directly in contact with the package leads from metal traces, through holes, ground, and power planes reduces the θJA . The expod paddle on the underside of the package must be soldered to a pad on the PCB surface that is thermally connected to a copper plane in order to achieve the specified θJA .
Figure 3 shows the maximum safe power dissipation in the package versus ambient temperature for the 24-lead LFCSP (70°C/W) package on a JEDEC standard 4-layer board with the underside paddle soldered to a pad that is thermally connected to a PCB plane. θJA values are approximations.
00.51.01.52.02.53.03.54.0–40
–20
02040
6080
04769-0-024
AMBIENT TEMPERATURE (°C)
M A X I M U M P O W E R D I S S I P A T I O N (W )
LFCSP
Figure 3. Maximum Power Dissipation vs. Temperature for a 4-Layer Board
ESD CAUTION
ESD (electrostatic discharge) nsitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features proprie-tary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
AD8133
Rev. 0 | Page 6 of 16
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
OPD V S––IN A +IN A
V S–OCM C S+S––OUT A V S +
–I N B
+I N B
V S –
V O C M A
V O C M B
+O U T A
V S +
+O U T B
–O U T B
V S +
+O U T C
04769-0-001
Figure 4. 24-Lead LFCSP
Table 5. Pin Function Descriptions
Pin No. Mnemonic Description 1 OPD Output Pull-Down 2, 5, 14, 21 V S−Negative Power Supply Voltage 3 −IN A Inverting Input, Amplifier A 4 +IN A Noninverting Input, Amplifier A 6 −OUT A Negative Output, Amplifier A 7 +OUT A Positive Output, Amplifier A 8, 11, 17, 24 V S+Positive Power Supply Voltage 9 +OUT B Positive Output, Amplifier B 10 −OUT B Negative Output, Amplifier B 12 +OUT C
Positive Output, Amplifier C 13 −OUT C Negative Output, Amplifier C 15 +IN C Noninverting Input, Amplifier C 16 −IN C Inverting Input, Amplifier C 18 V OCM C Voltage Applied to This Pin Controls Output Common-Mode Voltage, Amplifier C 19 V OCM B Voltage Applied to This Pin Controls Output Common-Mode Voltage, Amplifier B 20 V OCM A Voltage Applied to This Pin Controls Output Common-Mode Voltage, Amplifier A 22 +IN B Noninverting Input, Amplifier B 23 −IN B Inverting Input, Amplifier B
V OUT, dm
S+ PINS
S– PINS
04769-0-035
Figure 5. Basic Test Circuit
