NB4L52
2.5 V/
3.3 V/5.0 V Differential Data/Clock D Flip−Flop
with Ret
Multi−Level Inputs to LVPECL Translator w/ Internal Termination
The NB4L52 is a differential Data and Clock D flip−flop with a differential asynchronous Ret. The differential inputs incorporate internal 50 W termination resistors and will accept PECL, LVPECL, LVCMOS, LVTTL, CML, or LVDS logic levels. When Clock transitions from Low to High, Data will be transferred to the differential LVPECL outputs. The differential Clock inputs allow the NB4L52 to also be ud as a negative edge triggered device. The device is houd in a small 3x3 mm 16 pin QFN package. Features
•Maximum Input Clock Frequency > 4 GHz Typical
•330 ps Typical Propagation Delay
•145 ps Typical Ri and Fall Times
•Differential LVPECL Outputs, 750 mV Peak−to−Peak, Typical •Operating Range: V CC= 2.375 V to 5.5 V with V EE= 0 V •Internal Input Termination Resistors, 50 W •Functionally Compatible with Existing 2.5 V/3.3 V/5.0 V LVEL, LVEP, EP, and SG Devices
•−40°C to +85°C Ambient Operating Temperature
•The are Pb−Free Devices*
*For additional information on our Pb−Free strategy and soldering details, plea download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
MARKING DIAGRAM*
<
QFN−16
MN SUFFIX
CASE 485G
A= Asmbly Location工作狂英文
L= Wafer Lot
Y= Year
W= Work Week
工程部经理
G= Pb−Free Package
*For additional marking information, refer to
Application Note AND8002/D.
See detailed ordering and shipping information in the package dimensions ction on page 7 of this data sheet.
ORDERING INFORMATION
1
VTD
VTCLK
D
CLK
R D CLK Q
H x x L
L L Z L
L H Z H
Z = LOW to HIGH Transition
x = Don’t Care
Table 1. TRUTH TABLE
Figure 1. Logic Diagram
D
VTD
CLK
VTCLK
(Note: Microdot may be in either location)
R Figure 2. Pinout (Top View)
D D V TD
V TD V Expod Pad (EP)
Table 2. PIN DESCRIPTION
Pin Name I/O Description
1V TD −
Internal 50 W Termination Pin. (See Table 4)2D ECL, CML, LVCMOS,LVDS, LVTTL Input Noninverted Differential Input. (Note 1)3D ECL, CML, LVCMOS,LVDS, LVTTL Input
Inverted Differential Input. (Note 1)
4V TD −Internal 50 W Termination Pin. (See Table 4)5V TCLK −
Internal 50 W Termination Pin. (See Table 4)6CLK ECL, CML, LVCMOS,LVDS, LVTTL Input Noninverted Differential Input. (Note 1)7CLK ECL, CML, LVCMOS,LVDS, LVTTL Input
Inverted Differential Input. (Note 1)
8V TCLK −Internal 50 W Termination Pin. (See Table 4)9V EE −Negative Supply Voltage
10Q ECL Output Inverted Differential Output. Typically terminated with 50 W resistor to V CC − 2.0 V.11Q ECL Output
Noninverted Differential Output. Typically terminated with 50 W resistor to V CC − 2.0 V.12V CC −Positive Supply Voltage
13V TR −
Internal 50 W Termination Pin. (See Table 4)14R LVECL, LVCMOS,LVTTL Input Noninverted Differential Ret Input. (Note 1)15R LVECL, LVCMOS,LVTTL Input
Inverted Differential Ret Input. (Note 1)16V TR −Internal 50 W Termination Pin. (See Table 4)
−
EP
−
The Expod Pad (EP) on the QFN −16 package bottom is thermally connected to the die for improv
ed heat transfer out of package. The pad is not electrically connected to the die,but is recommended to be electrically and thermally connected to V EE on the PC board.
1.In the differential configuration when the input termination pin (VTD, VTD, VTR, VTR, VTCLK, VTCLK) are connected to a common termination voltage or left open, and if no signal is applied on D/D,CLK/CLK,R/R input then the device will be susceptible to lf −oscillation.
Table 3. ATTRIBUTES
Characteristic Value
ESD Protection Human Body Model
Machine Model
Charged Device Model > 2 kV > 200 V > 1 kV
Moisture Sensitivity (Note 2)Pb Pkg Pb−Free Pkg
QFN−16Level 1Level 1
Flammability Rating Oxygen Index: 28 to 34UL 94 V−0 @ 0.125 in
Transistor Count164
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
2.For additional information, e Application Note AND8003/D.
Table 4. MAXIMUM RATINGS
Symbol Parameter Condition 1Condition 2Rating Unit V CC Positive Power Supply V EE = 0 V 6.0V V EE Negative Power Supply V CC = 0 V−6.0V
V IO Positive Input/Output
Negative Input/Output V EE = 0 V
V CC = 0 V
V I v V CC
V I w V EE
6.0
−6.0
dixV
V
I IN Input Current Through R T (50 W Resistor)Static
Surge 45
80
mA
mA
I out Output Current Continuous
Surge 25
50
mA
mA
T A Operating Temperature Range−40 to +85°C T stg Storage Temperature Range−65 to +150°C
q JA Thermal Resistance (Junction−to−Ambient)0 LFPM
500 LFPM 16 QFN
16 QFN
42
35
°C/W
°C/W
q JC Thermal Resistance (Junction−to−Ca)2S2P (Note 3)16 QFN 4.0°C/W T sol Wave Solder Pb−Free265°C Stress exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stress above the Recommended Operating Conditions may affect device reliability.
3.JEDEC standard multilayer board − 2S2P (2 signal, 2 power) with 8 filled thermal vias under expod pad.
Table 5. DC CHARACTERISTICS, CLOCK INPUTS, LVPECL OUTPUTS
(V CC = 2.375 V to 5.5 V, V EE = 0 V or V CC = 0 V, V EE = −2.375 to −5.5 V, T A = −40°C to +85°C)
Symbol Characteristic Min Typ Max Unit I EE Power Supply Current (Inputs and Outputs Open)1625mA
V OH Output HIGH Voltage (Note 4, 5)
V CC = 5.0 V
V CC = 3.3 V
V CC = 2.5 V V CC− 1145
3855
2155
1355
V CC− 1020
3980
2280
1480
V CC− 895
4105
2405软件培训班
1605
mV
V OL Output LOW Voltage (Note 4, 5)
V CC = 5.0V
V CC = 3.3V
V CC = 2.5V V CC− 1945
3055
1355
555
V CC− 1770
3230
1530
730
reuters
V CC− 1600
3400
1700
900
mV
DIFFERENTIAL INPUT DRIVEN SINGLE−ENDED (Figures 4 & 7)
Vth Input Threshold Reference Voltage Range (Note 6)1050V CC− 150mV V IH Single−ended Input HIGH Voltage Vth + 150V CC mV V IL Single−ended Input LOW Voltage V EE Vth − 150mV DIFFERENTIAL INPUT DRIVEN DIFFERENTIALLY (Figures 5, 6 & 8 )
V IHD Differential Input HIGH Voltage1200V CC mV V ILD Differential Input LOW Voltage V EE V CC− 150mV V CMR Input Common Mode Range (Differential Configuration) (Note 7)1125V CC – 75mV V ID Differential Input Voltage (V IHD− V ILD)150V CC mV I IH Input HIGH Current D / D, CLK / CLK, R /R(VTx/VTx Open)−150150m A
I IL Input LOW Current D / D, CLK / CLK, R /R(VTx/VTx Open)−150150m A
R TIN Internal Input Termination Resistor405060W NOTE:Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transver airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding the conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously.
4.LVPECL outputs loaded with 50 W to V CC – 2.0 V for proper operation.
5.Input and output parameters vary 1:1 with V CC.
6.V th is applied to the complementary input when operating in single−ended mode.
7.V CMRMIN varies 1:1 with V EE, V CMRMAX varies 1:1 with V CC. The V CMR range is referenced to the most positive side of the differential input
signal.
Table 6. AC CHARACTERISTICS V CC = 2.375 V to 5.5 V; V EE = 0 V or V CC = 0 V, V EE = −2.375 to −5.5 V (Note 8)
Symbol Characteristic
−40°C
25°C 85°C Unit Min Typ Max
Min Typ Max
Min Typ Max
V OUTPP
Output Voltage Amplitude (@ V INPPmin ) (Note 10) (See Figure 4)f in v 2.0 GHz
f in v 3.0 GHz f in v 4.0 GHz 530490380770720580530490380780730580530490380760680530mV
sigma aldricht PLH ,t PHL Propagation Delay to CLK to Q, R to Q
Output Differential 300400
500300400
500300400
上海海关学院分数线500ps t s Setup Time 100100100ps t h Hold Time 505050ps t RR Ret Recovery 400400400ps t PW Minimum Pul Width
R/Rhonor什么意思
250
250
250
ps t JITTER
RMS Random Clock Jitter (Note 9)
f in v 2.0 GHz f in v 3.0 GHz f in v 4.0 GHz
111
111
111
ps
V INPP Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 10)150280015028001502800mV t r t f
翻译设备Output Ri/Fall Times @ 0.5 GHz (20% − 80%)
80
135
190
80
145
190
80
155
190
ps
NOTE:Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transver airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding the conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously.
8.Measured by forcing V INPP (MIN) from a 50% duty cycle clock source. All loading with an external R L = 50 W to V CC – 2.0 V. Input edge rates 40 ps (20% − 80%).
9.Additive RMS jitter with 50% duty cycle clock signal.
10.Input and output voltage swing is a single −ended measurement operating in differential mode.
f in , CLOCK INPUT FREQUENCY (GHz)
Figure 3. Output Voltage Amplitude (V OUTPP ) vs.
Clock Input Frequency at Ambient Temperature (Typical).
overnight delivery
V O U T P P , O U T P U T V O L T A G E A M P L I T U D E (m V )(T Y P I C A L )
70060050040030020010004
1
2
8003
Figure 6. Differential Inputs Driven Differentially
V V IL
Figure 7. V th
Diagram Figure 8. V CMR Diagram
IH − V IL
OH (Q) − V OL (Q)
Figure 9. AC Reference Measurement
