防抖动Verilog HDL代码：
module stable_key(key,led,clk );
input key,clk;
output led;
reg key_last;
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reg [31:0] cnt;
reg led;
always @(podge clk)
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begin
if (key!=key_last)
cnt<=0;
el
if (cnt==50000000)// stable length
begin
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cnt<=0;
knowledge>disappointing led<=key;
end
el
cnt<=cnt+1;
priorikey_last<=key;
end
太傻网站endmodule
.........................................
module stable_key(led,clk,key);
input key,clk;
output led;
reg key_last;
reg led;
reg[31:0] cnt;
always @ (podge clk)
begin
if(key!=key_last)
cnt<=0;
el
if(cnt==1000000)
begin
cnt<=0;
四级答案 led<=key;
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end
el
cnt<=cnt+1;
key_last<=key;
end
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endmodule
