东南大学
模拟实训MPW流片报告
课题名称： 预放大再生比较器设计
姓名：
米勒鲁豫有约
学号： at的用法
吃豆豆2004 指导老师：
摘要
比较器是电子系统中应用较为广泛的电路之一。比较器的设计以开环高增益放大器的设计为基础。虽然和运算放大器相比，比较器的应用范围相对狭窄，但比较器仍在很多应用中不可或缺，befamiliarwith尤其在模数转换器(Analog-to-digital converters，简称 ADC)aloe中。比较器作为流水线型ADC的关键模块，其速度、功耗等性能对整个模数转换器的速度和功耗都有着至关重要的影响。
在各种比较器结构中，预放大再生比较器速度快、功耗低、失调电压小，被广泛应用于高速比较器。本文基于预放大再生理论，采用 TSMC 3.3V 0.35μm CMOS 工艺，设计一种适用于流水线型 ADC 的高速低功耗比较器电路。该比较器由前置放大器，比较器和SR锁存电路构成。经过Cadence软件下的Virtuoso平台对电路进行前仿真，比较器工作电压为3.3V，共模输入电压1.6V，在500MHZ的时钟频率下，能够实现精度为30uV的比较，功耗为5.6mW，传输时延为crazy是什么意思4ns，翻转电压0.4mV。
关键词：比较器，预放大锁存，高速低功耗
Abstract
Comparator is one of the most important units widely ud in electronic systems. The design of a comparator is bad on loop gain amplifier. Compared with amplifiers, comparators are not that widely ud, but it is really necessary especially in Analog-to-digital converters (ADC). The comparator is a crucial part of ADC. Its speed and power have great impact on the characteristic of the whole ADC.
怪哉翻译Being one of various architectures, preamplifier-latch is widely ud as high-speed comparator due to its high-speed, low-power and small offt voltage. Bad on preamplifier-latch comparator, adopted TSMC 0.13μm CMOS process, a high-speed, low-power comparator applied for pipelined-ADC is propod in this paper. This comparator consists of three blocks:pre-amplifier, comparator and SR latch. The pre-simulation超越自我英语短篇文章s u Virtuoso simulation of Cadence, the comparator’s work voltage is 1.8V, and common input voltage is 1.6V, the simulation results indicate that the resolution of the comparator is 30uV, transmission delay is less than 4ns and power dissipation is about 5.6mW under the 500MHZ clock.
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