Dual N-Channel 60-V (D-S) MOSFET
FEATURES
•Halogen-free According to IEC 61249-2-21
Available
•TrenchFET ® Power MOSFET
•New Low Thermal Resistance PowerPAK ®
Package
•Dual MOSFET for Space Savings
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Notes
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a. Surface Mounted on 1" x 1" FR4 board.
b. See Solder Profile (/ppg?73257). The PowerPAK SO-8 is a leadless package. Th
e end of the lead terminal is expod
copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the expod copper tip cannot be guaranteed and is not required to ensure adequate bottom side solder interconnection.
c. Rework Conditions: manual soldering with a soldering iron is not recommended for leadless components.
PRODUCT SUMMARY
V DS (V)R DS(on) (Ω)I D (A)60
0.075 at V GS = 10 V 4.60.100 at V GS = 4.5 V
4.0
ABSOLUTE MAXIMUM RATINGS T A = 25 °C, unless otherwi noted
Parameter
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Symbol 10 s
Steady State Unit Drain-Source Voltage V DS 60Vcreamcleanr
Gate-Source Voltage
V GS
± 20
Continuous Drain Current (T J = 150 °C)a
T A = 25 °C I D 4.6 3.0A T A = 70 °C
3.6
2.4
Puld Drain Current
I DM 15
Continuous Source Current (Diode Conduction)a I S 2.7
1.2
Single Avalanche Current L = 1.0 mH I AS 15Single Avalanche Energy E AS 11
mJ Maximum Power Dissipation a
T A = 25 °C P D 3.3 1.4W T A = 70 °C
2.1
0.9Operating Junction and Storage T emperature Range T J , T stg
- 55 to 150
°C
Soldering Recommendations (Peak T emperature)b, c
260
THERMAL RESISTANCE RATINGS
Parameter
Symbol T ypical
Maximum
Unit Maximum Junction-to-Ambient a t ≤ 10 s R thJA
29
38°C/W
Steady State 60
cave85Maximum Junction-to-Ca (Drain)
Steady State
R thJC 4.0
5.2
Notes:
a. Pul test; pul width ≤ 300 µs, duty cycle ≤ 2 %.
b. Guaranteed by design, not subject to production testing.
Stress beyond tho listed under “Absolute Maximum Ratings” may cau permanent damage to the device. The are stress ratings only, and functional operation of the device at the or any other conditions beyond tho indicated in the operational ctions of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
SPECIFICATIONS T J = 25 °C, unless otherwi noted
Parameter Symbol T est Conditions Min. T yp.Max.Unit
Static
Gate Threshold Voltage V GS(th) V DS = V GS , I D = 250 µA 13V Gate-Body Leakage
I GSS V DS = 0 V , V GS = ± 20 V
白宫木兰树将被砍± 100 nA Zero Gate Voltage Drain Current I DSS V DS = 60 V, V GS = 0 V 1µA V DS = 60 V , V GS = 0 V , T J = 55 °C
5
On-State Drain Current a
I D(on) V DS ≥ 5 V , V GS = 10 V 15momus>四月英语
A Drain-Source On-State Resistance a R DS(on) V GS = 10 V, I D = 4.6 A 0.0600.075ΩV GS = 4.5 V , I D = 4.0 A 0.0800.100
Forward T ransconductance a g fs V DS = 15 V , I D = 4.6 A 6S Diode Forward Voltage a V SD
I S = 2.7 A, V GS = 0 V
0.8
1.2V
Dynamic b
Total Gate Charge Q g V DS = 30 V , V GS = 10 V , I D = 15 A
1220
nC Gate-Source Charge Q gs 2Gate-Drain Charge Q gd 3.5
Gate Resistance R g 1.5Ω
Turn-On Delay Time t d(on) V DD = 30 V, R L = 2 Ω
I D ≅ 15 A, V GEN = 10 V , R g = 2.5 Ω7
20ns
Ri Time
t r 825Turn-Off Delay Time t d(off) 15
40Fall Time
t f 720Source-Drain Rever Recovery Time
t rr
I F = 2.7 A, dI/dt = 100 A/µs 30
60
TYPICAL CHARACTERISTICS 25 °C, unless otherwi noted
On-Resistance vs. Drain Current
TYPICAL CHARACTERISTICS 25 °C, unless otherwi noted
eleventh
TYPICAL CHARACTERISTICS 25 °C, unless otherwi noted
Normalized Thermal Transient Impedance, Junction-to-Ca
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of veral qualified locations. Reliability data for Silicon Technology and Package Reliability reprent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, e /ppg?72403.
