LATTICEDIAMOND软件使⽤说明
Lattice Diamond Tutorial
June 2012
Copyright
Copyright ? 2012 Lattice Semiconductor Corporation.
This document may not, in whole or part, be copied, photocopied, reproduced, translated, or reduced to any electronic medium or machine-readable form without prior written connt from Lattice Semiconductor Corporation.
awkwardlyTrademarks
Lattice Semiconductor Corporation, L Lattice Semiconductor Corporation (logo), L (stylized), L (design), Lattice (design), LSC, CleanClock, Custom Movile Device, DiePlus, E2CMOS, Extreme Performance, FlashBAK, FlexiClock, flexiFLASH, flexiMAC, flexiPCS, FreedomChip, GAL, GDX, Generic Array Logic, HDL Explorer, iCE Dice, iCE40, iCE65, iCEcable, iCEchip, iCEcube, iCEcube2, iCEman, iCEpro
g, iCEsab, iCEsocket, IPexpress, ISP, ispATE, ispClock, ispDOWNLOAD, ispGAL, ispGDS, ispGDX, ispGDX2, ispGDXV, ispGENERATOR, ispJTAG, ispLEVER, ispLeverCORE, ispLSI, ispMACH, ispPAC, ispTRACY, ispTURBO, ispVIRTUAL MACHINE, ispVM, ispXP, ispXPGA, ispXPLD, Lattice Diamond, LatticeCORE, LatticeEC, LatticeECP, LatticeECP-DSP, LatticeECP2, LatticeECP2M, LatticeECP3, LatticeECP4, LatticeMico, LatticeMico8, LatticeMico32, LatticeSC, LatticeSCM, LatticeXP, LatticeXP2, MACH, MachXO, MachXO2, MACO, mobileFPGA, ORCA, PAC, PAC-Designer, PAL, Performance Analyst, Platform Manager, ProcessorPM, PURESPEED, Reveal, SiliconBlue, Silicon Forest, Speedlocked, Speed Locking, SuperBIG, SuperCOOL, SuperFAST, SuperWIDE, sysCLOCK, sysCONFIG, sysDSP, sysHSI, sysI/O, sysMEM, The Simple Machine for Complex Design, TraceID, TransFR, UltraMOS, and specific product designations are either registered trademarks or trademarks of Lattice Semiconductor Corporation or its subsidiaries in the United States and/or other countries. ISP, Bringing the Best Together, and More of the Best are rvice marks of Lattice Semiconductor Corporation.
Other product names ud in this publication are for identification purpos only and may be trademarks of their respective companies.
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of any correction if such be made. LSC recommends its customers obtain the latest version of the relevant information to establish, before ordering, that the information being relied upon is current.
Type Conventions Ud in This Document
Convention Meaning or U
Bold Items in the ur interface that you lect or click. Text that you type into the ur interface.
Variables in commands, code syntax, and path names.
Ctrl+L Press the two keys at the same time.
Courier Code examples. Messages, reports, and prompts from the software. ...Omitted material in a line of code.
Omitted lines in code and report examples.
.
.
.
[ ]Optional items in syntax descriptions. In bus specifications, the brackets are required.
( )Grouped items in syntax descriptions.
{ }Repeatable items in syntax descriptions.
| A choice between items in syntax descriptions.
Contents
Lattice Diamond Tutorial 1
Learning Objectives1
Time to Complete This Tutorial2
生日快乐用英语怎么说System Requirements2
Accessing Online Help2
About the Tutorial Design2
About the Tutorial Data Flow2
Task 1: Create a New Project4
Task 2: Running Analysis Tools8
Task 3: Inspect Strategy Settings10
Task 4: Examine Resources11
Task 5: Set Timing and Location Assignments13
Task 6: Running Place and Route17
Task 7: Examine Post Place and Route Results18
Task 8: Adjust Static Timing Constraints and Review Results20 Task 9: Comparing Multiple Place and Route Runs21 Task 10: Running Export Utility Programs23
Task 11: Download a Bitstream to an FPGA24
Task 12: Convert a File Using Deployment Tool26
C ONTENTS
Lattice Diamond Tutorial
The next generation design tool for FPGA design, Lattice Diamond, is
designed to address the needs of high-density FPGA designers.
This tutorial leads you through all the basic steps of designing and
implementing a mixed VHDL, Verilog, and Edif design targeted to the Lattice
ECP3 device family. It shows you how to u veral process, tools, and
reports from the Lattice Diamond software to import sources, run design
analysis, view design hierarchy, and inspect strategy ttings. The tutorial
then proceeds to step through the process of adding and editing a strategy, specifying the synthes
is requirements, examining the device resources, tting timing and location assignments, and editing preferences to configure the filter to implement the design to the target device.
Learning Objectives
When you have completed this tutorial, you should be able to do the following:◆Set up a mixed VHDL, Verilog, and EDIF project
◆View and Analyze the design
◆Inspect Strategy Settings
◆Examine Design Resources
◆Set Timing and Location Assignments
◆Place and Route
◆Create an Implementation
◆Set an Active Implementation
◆Compare Multiple Place and Route Runs
◆Examine Post Place and Route Results
L ATTICE D IAMOND T UTORIAL:Time to Complete This Tutorial
Time to Complete This Tutorial
The time to complete this tutorial is about 60 minutes.
System Requirements
The following software is required to complete the tutorial:
◆Lattice Diamond software
◆(Optional) LatticeECP3 Versa Development Kit
Accessing Online Help
闪电侠第一季You can find online help information on any tool included in the tutorial at any time by choosing Help > Lattice Diamond Help.
About the Tutorial Design
The design in this tutorial consists of a Verilog HDL module, two VHDL module and one EDIF module. The design that you create is targeted to Lattice ECP3 device families.
About the Tutorial Data Flow
The following figure illustrates the tutorial data flow through the system. You may find it helpful to refer to this diagram as you move through the tutorial tasks.
L ATTICE D IAMOND T UTORIAL :About the Tutorial Data Flow
Tutorial Data Flow Design files
Translate & Map
Design
Manage Project
Analyze design?Yes No
Enter Design
Analyze Design
Synthesize Design
Analyze design?
[RTL]Analyze design?
Yes PAR Design
[EDIF]
[NCD]
Analyze or ECO
Yes ECO design ECO Design
Program Device
the readerNo No
ECO device?Yes
Analyze & ECO
Device No
Data file
design?Analyze El
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wagaL ATTICE D IAMOND T UTORIAL :Task 1: Create a New Project
Task 1: Create a New Project
Projects are ud to manage input files, preferences, and optimization options related to an FPGA implementation. While there are a number of tasks you can perform independent of a project, most designs start with creating a new project.
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To create a new project:
1.On Windows, lect the Lattice Diamond icon or Start > Programs > Lattice Diamond
2.0 > Lattice Diamond .
The Lattice Diamond Design Environment appears.
The initial layout provides a Start Page which provides a list of common
Project actions to open a pre-existing project to
run the New Project Wizard. Hyperlinks in the right pane of the Start Page
provide access to ur guides, reference material, and online resources
available from /doc/9d77956a31b765ce0508147c.html .
2.From the Start Page, click Project > New , or from the Diamond main
window choo File > New > Project
. You can also click the New icon
expiration
from the toolbar and then choo Project .
The New Project overview dialog box appears.
3.Click Next . The New Project dialog appears.
Note
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Several design entry and analysis features of Lattice Diamond are available
without a source file as part of the project, for example, you may wish to define
and generate an IP core or a microprocessor platform using the Diamond interface
and u the result later in one or more projects. Also the power analysis features
in Diamond do not require source files to perform estimation .
L ATTICE D IAMOND T UTORIAL:Task 1: Create a New Project
4.Specify Project name: mixedcounter
Note
File names for Diamond projects and project source files must start with a letter (A-Z, a-z) and must contain only alphanumeric characters (A-Z, a-z, 0-9) and underscores (_).
5. to specify a directory on your local PC other than the
Diamond installation directory, for example,
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