I N VE N TI V E
CONFIDENTIAL
Formal Verification Guide
Prototype | Implement | Verify
Agenda
• Equivalence Checking Refresh • Verification Guide
– RTL Design – Verifiable Synthesis Flow – Abort Resolution
• ECO Automation • Best Practice Recommendation
2
August 6, 2009
Cadence Confidential
Encounter Conformal Product Family
Verifies 100% of design functionality without requiring test vectors Provides independent verification for lowest risk silicon Validates CPF LP Equivalence Checking Verifies Low Power design implementation Performs structural and functional checks
vistEquivalence Checking
RTL or Gate RTL or Gate
Digital Custom Verification including Memories, Data Paths, and IO Orders of magnitude faster than simulation
入境是什么意思Low Power Verification
Functional Checks
v1
v2
ISO
A
日语mp3
B
Finds bugs earlier in the design cycle Verifies proper CDC synchronization to avoid clock related re-spins Creates safer EC environment建造师培训班
Validation, generation and analysis of constraints Us industry proven formal engines Shorter design cycle with improved timing constraints
Constraint Design
ECO Implementation
o1 o2
Provides automated RTL2GDS ECO solution Identifies and generates fix to implement ECO Interfaces with physical implementation tool flow
邮编英文缩写
3
brethren
August 6, 2009
Cadence Confidential和外国人聊天的网站
Encounter Conformal & FED Product Family
Equivalence Checking
RTL or Gate RTL or Gate
Constraint Design
Low Power Verification
Functional Checks
A耙子
Validation, generation & analysis of constraints Shorter design cycles with improved timing constraints
v 1
v2
ISO
B
100% Independent vector-less verification of implementation RTL Gate Transistor CDC & Ext Checkscookies
Structural and functional LP checks LP design implementation Verification LP Equivalence Checking
离骚翻译New Products ECO Implementation RC-Physical Synthesis Chip Planning Systems
o 1 o 2
Automated RTL2GDS ECO solution Identifies and generates ECO fix Physical Correlation & Predictability with final backend Congestion Analysis & Opto (Congestion Relief) Architectural & Economic Forecasting Lower IC Cost & Expedite TTM
4
August 6, 2009
Cadence Confidential
I N VE N TI V E
CONFIDENTIAL
Crash Cour on Equivalency Checking
Prototype | Implement | Verify
