专利名称：LDMOS using a combination of enhanced
dielectric stress layer and dummy gates
发明人：Sanford Chu,Yisuo Li,Guowei Zhang,Purakh
moonwalkingRaj Verma
申请号：US11488117
申请日：20060717
公开号：US07824968B2
公开日：
ccni
newhorizon20101102
国籍英语专利内容由知识产权出版社提供bestller
专利附图：
出生日期英语
摘要：First example embodiments compri forming a stress layer over a MOS transistor (such as a LDMOS Tx) comprid of a channel and first, cond and third
junction regions. The stress layer creates a stress in the channel and the cond junction region of the Tx. Second example embodiments compris forming a MOS FET and at least a dummy gate over a substrate. The MOS is comprid of a gate, channel, source, drain and offt drain. At least o吸血鬼日记2
ne dummy gate is over the offt drain. A stress layer is formed over the MOS and the dummy gate. The stress layer and the dummy gate improve the stress in the channel and offt drain region.
deepend申请人：Sanford Chu,Yisuo Li,Guowei Zhang,Purakh Raj Verma
七夕的英文
地址：Singapore SG,Singapore SG,Singapore SG,Singapore SG
国籍：SG,SG,SG,SG
代理机构：Horizon IP Pte Ltdjoan什么意思
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