Optoelectronic Multi-Chip Module Demonstrator System
Jason D. Bakos
Department of Computer Science, University of Pittsburgh
jbakos@cs.pitt.edu
Donald M. Chiarulli
Department of Computer Science, University of Pittsburgh
don@ee.pitt.edu
Abstract
characterMuch rearch has been conducted in the area of optoelectronic interconnection and packaging technology. Much of this work is an effort to develop high bandwidth and low latency optoelectronic chip-to-chip interconnection, or “optoelectronic multi-chip modules” (OE-MCM’s). Most current designs for optoelectronic OE-MCM technology suffer from problems caud by overly complex optical alignme
nt requirements, which prevent them from being commercially feasible. Our group’s contribution to this area involves the u of rigid imaging fiber bundles, which rve as both the interconnection medium and the packaging for chip-to-chip interconnections. Our demonstration architecture for this technology is an OE-MCM that implements a 64-channel non-blocking fiber optic crossbar switch. Each OE-chip implements 64 channels of optical input and output that are guided within the MCM by an optic built from two gments of image guide. The focus of this paper is the design of this demonstrator system.
1. Introduction
In previously published work [1, 2], we have prented a number of link architectures that demonstrate both short haul (multi-chip module) and board-to-board interconnection technology. We have shown that the designs have significant advantages over both conventional electronic MCM’s and free-space optical MCM’s, such as compact device geometry, relaxed alignment constraints, and a highly manufacturable monolithic packaging architecture. In such systems, it is possible to achieve large scale, den 2 dimensional arrays of data channels with per channel bandwidth of 10GHz or more (per simulation results). This degree of parallelism and speed is not possible with conventional electronics due many factors, such as parasitic capacitance inherent in su
ch systems. In this paper, we report our progress in constructing and characterizing a prototype for optoelectronic multi-chip-modules (OE-MCM). This prototype is a proof-of-concept demonstration that implements a 3-chip, 64-channel non-blocking fiber optic switch. The packaging and interconnect for this demonstrator is bad on the u of small gments of rigid imaging fiber bundles.
Section 2 provides a description of the chip that we designed for this demonstrator system. The chip was fabricated by Peregrine Semiconductor in their recently developed process, .5um ultra-thin silicon-on-sapphire (UTSi). Section 3 is an overview of the overall system architecture. Section 4 describes the current state of construction and testing of the demonstrator. Section 5 lists conclusions and future work. Section 6 lists references.
2. Switch Chip Design
Our demonstrator system consists of a 3-chip OE-MCM that makes up a
64 channel switch fabric. Each chip implements eight independent 8x8
switching elements. The enmble of the three chips is connected in a
武汉外语学校3 stage non-blocking CLOS switch network, as shown in Figure 1.
The chips themlves measure 4mm x 5.5mm and were fabricated as
part of the Peregrine ultra-thin silicon-on-sapphire (UTSi) COOP run.
The switch chips are laid out into three distinct ctions: the receiver
array (along with the modulation circuitry and area pads for the PIN
photodiode chip), the driver array (along with the driver circuitry and
area pads for the VCSEL chip), and the CMOS logic that imp lements
the 8 8x8 switching elements. Each switch output is t up as a three
stage 8-to-1 multiplexor (as shown in Figure 3). Stage one, along with
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its configuration memory, is located in the left half of the logic ction
of the chip. Stages two and t h ree, along with their configuration
Fig. 3. Switch Logic right half of the logic ction. Registers that hold the “cache” and “map” switch
configuration data for each output reprent the configuration memory for the outputs. Additional log
ic for loading and decoding the configuration data is distributed throughout the logic ction. Signal drivers, supply decoupling capacitors, and ECM protection are strategically placed throughout the chip. Alignment marks were created using
the top metal layer and placed throughout the chip to facilitate alignment when bonding the dies to the optic. This is possible due to the optical transparency of the die substrate. Figure 2 shows three different images of the switch chip. The first image is a floor-plan view of the chip, the cond is the CAD design of the chip, and the fourth is an image of the switch chip, bump -bonded to
both an 8x8 PIN photodiode chip and an 8x8 VCSEL (vertical cavity surface
emitting lar) chip. The switch logic is shown on the top half of the die. The
third image also shows the optical transparency of the sapphire die substrate.
Separate, 8x8 VCSEL and PIN-photodiode arrays are flip-chip (bump) bonded to the switch chips. 2.1. Flip-chip bonding Flip-chip bonding, or “bump bonding”, is a way to electrically connect two dies.
In this ca, the silicon switch chip must be bonded to two smaller (2 mm x 2 mm), gallium -arnide
chips: the 8x8 photodetector array (lar receiver) chip
and an 8x8 VCSEL array (lar emitter) chip. Both of the chips are
commercially available products. Rectangular area pads are placed on the top
metal layer on the switch chip and the receiver/lar chips. Gold or indium
struggle是什么意思soldier bumps (in a heated, liquid state) are placed on the area pads. The two
chips that are being bonded are then presd together such that the area pads on影视动漫培训学校
both chips are in contact. The solder bonds the chips together. Afterwards, the
chips are electrically connected through the area pads. The area pads on the
switch chip for both the receiver array chip and the VCSEL array chip are shown
in Figure 4.
The resulting OE chips were then bonded directly to an optical element built from
two gments of rigid fiber image guides. The fiber bundles guide all of the
optical signals between the chips without additional optical elements. Optical
input and output is implemented with a pair of 2D (8x8) fiber ribbon cables that
are also directly bonded to the image guide optic.
2.2. Printed Circuit Board Design
Electrical connections are made via bump bonds between the UTSi devices and
conventional printed circuit boards on which the MCM is mounted. The circuit
board ud for the switch chips provides the electrical connections for
Fig. 2. From left: Floorplan of switch chip, showing the relative locations of each portion of the chip. CAD design of chip layout. Photograph of fabricated chip. The chip is a 64 channel transceiver/switch chip designed at the University of Pittsburgh and fabricated by Peregrine. 8x8 PIN detector and VCSEL arrays are shown flip to the device.
Fig. 4. Images of the flip -chip bond pads
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configuration, which are brought off-board using electrical ribbon cables. The circuit board also provides trim-pot adjustable voltage regulation for the power and bias supplies. The chip design includes multiple ways to perform testing of its receivers and drivers, and the chip’s interface for the test I/O is connected to SMA connectors on the printed circuit board. We designed two generations of the boards, which were fabricated by local companies.
2.3. Switch Configuration
The switch is configured electrically and requires 192 bits of configuration data. This information is stored in a two-level configuration memory. The “map” level of the configuration memory drives the configuration of the switch logic. The “cache” level is a cond copy of the configuration loaded externally through the electrical interface. To conrve I/O pins the cache level is loaded over multiple cycles of a 12-bit I/O bus. Once a new configuration is
Fig. 6. Wireframe view of switch architecture.
贯彻的意思Fig. 7. Outside view of the OE-MCM, from the top and bottom.
深圳远程教育Fig. 8. OE-MCM demonstrator a core-per-channel arrangement such as you have in a fiber ribbon cable. In the past, we have demonstrated a 16 channel interconnect between two VCSEL/detector arrays that were directly butt coupled to an imaging fiber bundle with no other optical elements ud in the tup. Crosstalk between the channels was low, -22db, and loss mechanisms were largely characterized by inrtion loss corresponding to the fill factor of the bundle.
As can be en by Figures 6 and 7, a chip is mounted on a two ction fiber image guide. The left half of the chip is on top of the ction where the fibers run orthogonal to the chip surface. The right half of the chip is on top of the ction where the f ibers run 70 degree off the chip surface. This is s是什么意思
hown in the bottom view of the fiber image guide. The side view of the optic shows the fiber direction.
Figure 5 shows an image of the image guide optic. The dark region on the
top of the optic exists becau the fiber direction caus the side wall of
the optic to be imaged. The dark region on the bottom of the optic exists
becau the fiber direction caus the opposite side wall of the optic to be
imaged (where the two pieces of image guide meet).
For the OE-MCM design prented in this paper, OE chips are directly
bonded to the end surface of the fiber bundle such that optical signals
traver to transparent silicon-on-sapphire substrate and are coupled into
the fiber guide. Since the fiber bundle gments are rigid, the waveguides
become both the structural elements and the communication channels.
There are veral other advantages to this approach over other types of OE
interconnection structures. There are no global alignment constraints.
Each device needs only to be passively aligned to the package. Since all
parts of the systems are directly bonded to one another, the package is far
more tolerant to thermal and mechanical stress. Minimum size systems can be designed, using three dimensions to minimize the time of flight
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latency.
Figure 6 is a wireframe view of the system that depicts the three OE-chips and 2D fiber arrays mounted on the image guide optic. Note that the optic is built from two gments that are distinguished by the orientation of the internal fibers shown by the dotted lines. In the smaller gment, the fibers in the image guide run vertically and are normal to the imaging surfaces. In the larger gment, shown below Chip #2, the image guide is cut such that the fibers run at a 20 degree offt. This offt is required becau the location of the VCSEL and detector arrays on the switch-chips is not symmetrical relative to the chip axis. The required orientation of the arrays in chip #2 pla
ces the switching logic between the arrays and the fiber ferrule. This introduces an offt relative the arrays in chips #1 and #3 that is compensated by the bias in the fiber direction. Note that chip #1 and chip #3 are turned by ninety degrees relative to the fiber ferrule and chip on the top surface. The corner-turns implement spatially the interconnection pattern for the 3-stage CLOS network. As shown in this diagram, optical signals enter the switch via one of fiber ribbons and traver the vertically cut image guide to the detector array on chip #1. Signals are switched by row to particular VCSEL on chip #1 where they re-enter image guide optic, this time in the 20 degree bias cut gment. This gment images the signals on the detector array of chip #2 which performs the cond stage switching operation after which the signals re-enter the bias cut gment. Chip #3 performs the final switching operation to direct the signal to output fiber channel. The signal enters the outgoing ferrule through the vertically cut image guide between chip #3 and the output ferrule. Note that chip #1 and chip #3 are turned by ninety degrees relative to the fiber ferrule and chip on the top surface. The corner-turns implement spatially the interconnection pattern for the CLOS network. The completed electrical and mechanical tester OE-MCM for the demonstrator system is shown in Figure 8. The ribbon cables are ud to configure the three switch chips. Large heat sinks are ud to dissipate the heat generated by the switch chips and the voltage regulators on the printed circuit boards.
4. Test Results and Current Status
Using one of the switch chip dies that has had a receiver array bump bonded to the receiver ction, we performed receiver tests though the fiber image guide. We performed this test by directly coupling a fiber ferrule to one end of the fiber image guide. A 500MHz random bit lar pattern was imaged through the optics onto one of the PIN diode receivers bonded onto the switch chip. The incoming signal was sampled electronically from one of the tester outputs on the chip. The eye diagram from the output of this operation is shown in Figure 9. This experiment
half of the tester die. The results obrved characterize
the signaling path from the lar source, through the
image guide, and into the logic ction.
We have also ud the test functionality of the chip to
stimulate the VCSEL drivers with data from the
configuration memory. By electronically changing the
configuration memory while the chip is in test mode,
we have measured data rates from the VCSEL area pads
at 500MHz.
The bandwidth limitation is primarily due to limitations
on the probing system. We anticipate that the system
will operate at 1-2 Gbs when bonded to PCB boards.
5. Conclusions and Future Work
This prototype tests some of basic technology for image guide bad OE-MCM devices. Future work will involve implementing more advanced MCM architectures, such as a processor to memory interconnection. Also, additional logic in the UTSi chips will add channel coding and error correction to the transceivers, creating a “smart transceiver”.
6. References
1. Jason D. Bakos, Donald M. Chiarulli, and Steven P. Levitan, "Optoelectronic Multi-Chip-Module Implementation of a 64-Channel Fiber Switch," 2002 International Topical Meeting on Optics in Computing 200
2. pp 161-16
3.
2. Jason D. Bakos, Donald M. Chiarulli, “Design of a Crossbar Switch Chip for U in a Demonstration System of
an Optoelectronic Multi-Chip Module”, DAC 2002 Student Design Contest 2nd place winner (conceptual category).
