little by little
基于STC89C51和CPLD实现的DDS与频率计
键盘输入 DDS
STC89C51
LCD1602显示电路 频率计
系统框图
功能描述：以STC89C51为控制核心，实现任意频率值fa（小于10KHz）的输入，经单片机出来后，生成相应的频率字，然后送给DDS模块，DDS模块开始工作，生成以频率值fs；但键盘测频键按下后，单片机控制频率计，让其开始控制，频率计输出值送回单片机处理，得出测量到的频率值fc，最后单片机控制LCD1602显示人为输入的频率值fa和频率计测得的频率值fc，两个值的差异可以直观的显示出系统的误差。
基于CPLD/FPGA的DDS原理图如下：
基于CPLD/FPGA的频率计的原理图如下：
DDS模块代码：
（1）MUX832
开票员岗位职责LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY MUX832 IS
PORT( DATAINN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
clk : in std_logic;
DATAOUTT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
SELL :IN STD_LOGIC_VECTOR(1 DOWNTO 0));
END MUX832;
ARCHITECTURE behav OF MUX832 IS
BEGIN
PROCESS(SELL,DATAINN,clk)
BEGIN
if clk'event and clk='1' then
CASE SELL IS
WHEN "00" => DATAOUTT(7 DOWNTO 0) <= DATAINN;
WHEN "01" => DATAOUTT(15 DOWNTO 8) <= DATAINN;
WHEN "10" => DATAOUTT(23 DOWNTO 16) <= DATAINN;
WHEN "11" => DATAOUTT(31 DOWNTO 24) <= DATAINN;the great wall
英语翻译器在线翻译
END CASE;
end if;
END PROCESS;
END behav;
（2）32位加法器
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
foroverENTITY ADDER32B IS
PORT ( A: IN STD_LOGIC_VECTOR(31 DOWNTO 0);
B: IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S: OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
END ADDER32B;
ARCHITECTURE behav OF ADDER32B IS
BEGIN
S<=A+B;
END behav;
（3）32位寄存器
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY REG32B IS
PORT( LOAD : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
END REG32B;
ARCHITECTURE behav OF REG32B IS
BEGIN
PROCESS(LOAD,DIN)
begin
breakaway歌词
IF LOAD'EVENT AND LOAD ='1' THEN
DOUT<=DIN;
END IF;
END PROCESS;
END behav;
频率计模块代码：
（1）标准频率计数器
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY BZHH IS
PORT (BCLK: IN STD_LOGIC; --Fs
BENA: IN STD_LOGIC;
CLR : IN STD_LOGIC; --清零
BZQ : inOUT STD_LOGIC_VECTOR(31 DOWNTO 0));
END BZHH;
ARCHITECTURE behav OF BZHH IS
BEGIN
PROCESS(BCLK, CLR) --标准频率计数开始
BEGIN
IF CLR = '1' THEN BZQ <= (OTHERS=>'0');
ELSIF BCLK'EVENT AND BCLK ='1' THEN
IF BENA ='1' THEN BZQ <= BZQ + 1;
END IF;
END IF;
END PROCESS;
END behav;
（2）待测频率计数器
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY TTFF IS
PORT (TCLK: IN STD_LOGIC; --Fs
作文模板 ENA: IN STD_LOGIC;
CLR : IN STD_LOGIC; --清零
TSQ : inOUT STD_LOGIC_VECTOR(31 DOWNTO 0));
END TTFF;
ARCHITECTURE behav OF TTFF IS
BEGIN
PROCESS(TCLK, CLR,ENA)
BEGIN
IF CLR = '1' THEN TSQ <= (OTHERS=>'0');
ELSIF TCLK'EVENT AND TCLK ='1' THEN
IF ENA ='1' THEN TSQ <= TSQ + 1;
END IF;
END IF;
END PROCESS;
END behav;
（3）MUX648
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY MUX648 IS
PORT( DATAIN1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DATAIN2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DATAOUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
SEL :IN STD_LOGIC_VECTOR(2 DOWNTO 0));
END MUX648;
ARCHITECTURE behav OF MUX648 IS
BEGIN
DATAOUT <= DATAIN1(7 DOWNTO 0) WHEN SEL="000" ELSE --标准频率计低八位输出
DATAIN1(15 DOWNTO 8) WHEN SEL="001" ELSE
DATAIN1(23 DOWNTO 16) WHEN SEL="010" ELSE
DATAIN1(31 DOWNTO 24) WHEN SEL="011" ELSE --标准频率计最高八位输出
DATAIN2(7 DOWNTO 0) WHEN SEL="100" ELSE --待测频率计数值低八位输出
DATAIN2(15 DOWNTO 8) WHEN SEL="101" ELSE
DATAIN2(23 DOWNTO 16) WHEN SEL="110" ELSE
DATAIN2(31 DOWNTO 24) WHEN SEL="111" ELSE --待测频率计数值最高八位输出
DATAIN2(31 DOWNTO 24) ;
END behav;
单片机程序如下：
主程序men
#include<reg52.h>
#include<intrins.h>
#include"key.h" //scankey(); keyexe(); tfre(); testfre();
#include"lcd1602.h" //display();
insistsvoid main(void)
{
lcd_init();
bena=0;
clr=1;
load_dds=0;
草莓的英文单词
oe=0;
start=1;
lcd_str(0,2,"stfre!");
while(1)
{
keyexe();
}
}
键盘程序：
#ifndef __KEY_H__
#define __KEY_H__
#include<reg52.h>
#include<intrins.h>
#include "lcd1602.h"
#define dinout P3;
unsigned char keybuffer[8],longtochar[4],recieve[8];
unsigned long freword,tdispbuf;
