Overview of Formality Labs for
Debugging Failing Verifications
Purpo: The labs are designed for you to find, analyze, and solve common equivalency checking problems using Formality. You can u the labs to increa your awareness of Formality and to practice debugging skills.
Content: The labs u public-domain RTL source. The netlists were generated using Design Compiler F-2011.09 relea software. Procedure:
∙There is a README file for every lab describing what to do.
∙Each lab has a “runme.fms” FM Tcl script you can u initially.
∙Each lab has a “hint” directory containing a README file if you need some helpful pointers on what to do.
∙If you find that a lab is too difficult, there is a “.solution”
sub-directory with the correct solution.
∙Plea compare your results with the correct results when you finish each lab.
∙This lab document will guide you through each lab.
Invoke Formality in this manner:
"fm_shell -gui -f runme.fms |tee runme.log" or
"formality -f runme.fms |tee runme.log"
FM Lab1: Missing Verification Files Objective: This lab shows an example of what happens in verification
if pieces of the reference and implementation designs are missing and更好地
if guidance is missing. The focus of this lab is to review transcript messages. You need to change the "runme.fms" FM Tcl script to get a successful verification.
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Lab flow:
1.) Run the verification using the existing "runme.fms" script.
2.)Finding clues to indicate potential problems:
2a) Transcript messages:
Formality debugging involves collecting information that may point to the reason why the design fails verification. Always look at the transcript messages first.
Note the following warning messages in the transcript:
Status: Creating
Created technology library 'FM_BBOX' in container 'r' for black-box designs
Created black-box design 'mAlu' in library 'FM_BBOX'
Warning: 1 blackbox designs were created for missing references. (FM-064)
Status: Attempting to resolve unlinked cells by
Warning: 150 black-box pins of unknown direction found; e formality.log for list (FM-230)
Top design t to 'r:/WORK/mR4000' with warnings
Formality is creating a black-box in the reference design to reprent a missing piece of the design. The missing piece is “mAlu”. Perhaps
an engineer forgot to nd over that portion of the RTL, or merely left it out of the FM Tcl script.
This transcript message is only a warning instead of an error becau the customer included this variable tting in the FM TCL script: t hdlin_unresolved_modules black_box
铜活Otherwi, by default Formality would have stopped processing the design.
When faced with a missing piece of the reference design, you can either find the missing piece and try verification again. Or, you can try to black-box the equivalent sub-design in the implementation design, if
the hierarchy was retained during synthesis.
3.) For this lab, you can find the missing RTL by quickly browsing in the “rtl” sub-directory and include the missing file in your FM Tcl script. Re-run verification.
4.) After running verification again, notice that the transcript still has the messages:
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t_top i:/WORK/mR4000
报偿的意思Setting top design to 'i:/WORK/mR4000'
Warning: Cannot link cell '/WORK/mR4000/DP_OP_94J1_124_8045_U32' to its reference design 'fa2a0'. (FE-LINK-2)
Warning: Cannot link cell '/WORK/mR4000/DP_OP_94J1_124_8045_U31' to its reference design 'fa1b0'. (FE-LINK-2)
Warning: Cannot link cell '/WORK/mR4000/DP_OP_94J1_124_8045_U30' to its reference design 'fa2a0'. (FE-LINK-2)
Warning: Cannot link cell '/WORK/mR4000/DP_OP_94J1_124_8045_U29' to its reference design 'fa1b0'. (FE-LINK-2)
Warning: Cannot link cell '/WORK/mR4000/DP_OP_94J1_124_8045_U28' to its reference design 'fa2a0'. (FE-LINK-2)
英语六级及格线Warning: Cannot link cell '/WORK/mR4000/DP_OP_94J1_124_8045_U27' to its reference design 'fa1b0'. (FE-LINK-2)
Warning: Cannot link cell '/WORK/mR4000/DP_OP_94J1_124_8045_U26' to its reference design 'fa2a0'. (FE-LINK-2)
Warning: Cannot link cell '/WORK/mR4000/DP_OP_94J1_124_8045_U25' to its reference design 'fa1b0'. (FE-LINK-2)
This indicates that Formality cannot find veral library component
cells for the implementation design. Formality is creating black-boxes for them. This is a sign that a library is missing from the tup. 5.) Since verification already ran, i f you run the “Analyze” command, Formality will indicate that there are unmatched black-box nets in the implementation design that do not exist in the reference design. This
is another indication of something missing in the implementation design.
6.) Find the missing library and include it in the FM Tcl script. Re-run verification.
7.) During this verification run, Formality located all of the design pieces and library information. However, verification is still
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failing. The only clue for this issue is the following statement in
the transcript:
Info: Formality Guide Files (SVF) can improve verification success by automating tup.
You need to include the SVF guidance file in the FM Tcl script: t_svf mR4000.svf
8.) Since there is no clock-gating nor scan involved, there is no additional tup needed. Auto tup mode is not required.
9.) Try verification again. You should now get a successful
verification.
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9.) You can automatically create a FM Tcl script by using UNIX command “fm_mk_script”. Try the following:
fm_mk_script mR4000.svf
10.)View the resulting FM Tcl script “fm_l”, and try it out with Formality.
FM Lab2: Synthesis Pragmas
Objective: This lab contains Verilog RTL using Synopsys Parallel Ca and Full Ca synthesis pragmas. You must change the "runme.fms" FM TCL script to get a successful verification.
Lab flow:
1.) Run the verification using the existing "runme.fms" script.
2.)Find clues to indicate potential problems.
2a) Transcript messages:
Formality debugging involves collecting information that may point to the reason why the design fails verification. Always review the transcript messages first.
Note the following warning message in the transcript:
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************ RTL Interpretation Summary ************
************ Design: r:/WORK/mR4000
full_ca ignored (7 total, 1 with unspecified cas)
parallel_ca ignored (7 total, 1 with overlapping cas)
Plea refer to the Formality log file for more details,
or execute report_hdlin_mismatches.
****************************************************
This is our first clue that there may be simulation/synthesis mismatches due to specifying full ca and parallel ca pragmas in the RTL.
2b) Messages from analyze_point commands:
Under the Debug tab, run "Analyze". Formality knows that the logic cones are different, but cannot pinpoint the specific problem.
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