PR883: A 300-W, Universal Input, Isolated PFC Power Supply for LCD TV Applications
Power Management – Power Supply Controllers
1 INTRODUCTION
This guide documents a low-profile power supply that is suitable for powering LCD TVs or other flat screen applications. The power supply accepts a universal AC line-input voltage (85 VRMS to 265 VRMS), and produces an output voltage of 24-VDC for loads up to 12 A (288 W).
The requirements for a flat-panel display include a physical profile and the ability to operate from the ac-line input at clo to unity power factor. Therefore a flat-panel display application demands that an internal power supply be thin so as to fit behind the screen inside the TV ca, and comply with the power quality requirements defined in the IEC standard, 61000-3-2. In addition, the combination of a tight physical package and the desire to meet Energy Star® guidelines requires that the design also demonstrates very high efficiency. Described herein is a practical design that us standard components. It achieves the requirements using a traditional two-stage power converter topology along with state-of-the-art power circuit control methods. The first stage is an interleaved, transition-mode, power factor correcting (PFC) boost pre-regulator. This is followed by an isolated LLC ries-resonant
DC-DC main converter.
The design takes advantage of three integrated circuit (IC) power controllers. The PFC pre-regulator stage is controlled by the UCC28061, a dual-pha, interleaved, transition-mode PFC controller. The resonant LLC converter us the UCC25600; a low-cost 8-pin controller. The third IC is the UCC2813D-4. This is ud to control a small 5-W flyback converter that provides a bias supply voltage. The bias supply is optional. It is provided for convenience so that the circuit can be demonstrated without the need for a bench supply.
2 SCOPE
A reference design is primarily intended to demonstrate the design of a functional circuit, the operation of which has been verified through a limited number of performance tests. This circuit incorporates esntial safety features. The include an input line fu, inrush current control, output over-current limit, and output over-voltage protection. An area not addresd by this design is electromagnetic compatibility (EMC). For most applications, EMI filter components would need to be added so that the design meets applicable environmental and system compatibility requirements. To comply with EMC standards, components such as input and output filters would be required to suppr
ess electromagnetic interference (EMI). In addition components that suppress and/or protect the unit from high-voltage line surges and lightening would be required to meet power quality and safety standards.
3 ELECTRICAL PERFORMANCE
Table 1 Performance Specifications
&
Conditions Min Nom Max Units Symbol Parameter Notes
INPUT CHARACTERSTICS
V I Input Voltage 85 265 VRMS Frequency 48 65 Hz
f Line
I I Input Current 4 ARMS
p.f. Power
Factor 0.95
OUTPUT CHARACTERSTICS
Stage:
PFC
Vo (HVDC)Output Voltage 390 VDC
Stage:
LLC
Resonant
Vi (HVDC)Input Voltage 330 410 VDC V O Output Voltage 22.8 24 25.2 V
I O Output Current 1 1 12 A
W P O Output Power 288
I LIM Current Limit ΔV O = -4 V 20 A
Regulation %V O
ΔV LOAD Load
SYSTEM CHARACTERSTICS
ηFull Load Efficiency 110 VAC, 80% load 87 %
t HOLD Hold-up Time Nominal V I, 80% load 40 ms
OV THLD Over-Voltage Threshold OV shutdown and restart 30 V
thickness 20 mm Overall
Temp. Range Nat’l Conv. airflow 0 50 °C
acting 5 A Fu
Rating Fast
Notes:
1. Operates down to zero load with reduced regulation.
4 DESCRIPTION
Fig. 1 shows the circuit divided into three blocks. Each block reprents one of the three converters that make up the complete power system. They include the boost PFC pre-regulator, the LLC ries-resonant DC-DC converter, and the 5-W bias supply. The PFC boost pre-regulator operates off a universal ac-line input voltage and produces a regulated 390 VDC output. The output from this stage is fed to both the main LLC resonant and bias supply converters. The bias supply provides a regulated 15 VDC to power the control circuitry, and the LLC resonant converter produces an isolated output that is regulated at 24 VDC. For each of the three circuits, the theory of operation is described.
Fig. 1 LCD TV Power System Block Diagram
4.1 Boost PFC Pre-Regulator
The principle function of the boost PFC pre-regulator is to convert a wide-input voltage (universal) ac-line input source to a regulated DC voltage, while operating at near unity power factor. It achieves this by controlling the power MOSFET of a boost converter at a relatively constant ‘on’ time over each half period of the rectified ac input. Applying a constant ‘on’ time to each switch period caus the current in the boost inductor to ri proportionally to the applied input voltage. As the current in the inductor is equal to the input current, then the average switched current drawn from the input source is proportional to the source voltage. In this condition the input of the circuit appears as a pure resistance and the circuit operates at unity power factor. To maintain boost converter operation, the regulated output voltage is t at 390 VDC. This voltage must be higher than the peak of the maximum input ac rms voltage, which is 375 V. The output capacitance to the boost PFC converter is relatively large. This is becau a large frequency component of the inductor ripple current is at just twice the minimum line frequency (94 Hz).
The circuit prented in this design is similar to that described in the UCC28060 evaluation module (UCC28060EVM). It includes a number of operating refinements to the basic boost PFC converter concept. The design us two boost inductors and MOSFET switches. The are connected in parall
el to form two phas that feed the common output capacitance. During normal operation the MOSFETS are operated 180° out of pha to each other, such that they are electrically interleaved. As a further enhancement the boost inductors are operated
in “transition mode.” With this technique the current in each inductor is required to completely decay to zero during the ‘off’ period of the transistor switch before the next ‘on’ period is initiated. Zero inductor current is detected by the control circuit using an auxiliary winding on each inductor. The voltage across the auxiliary winding collaps to zero when the inductor energy is exhausted. The combination of interleaved phas and transition-mode control results in improved efficiency and smaller component sizes when compared to a traditional single-pha solution. The and other control enhancements, such as pha management and input current shaping, are built in to the boost PFC control IC. This design us the UCC28061 controller. The UCC28061 has improved audible noi performance over the UCC28060. In addition the pha management of the UCC28060 is determined purely by the total ‘on’ time demanded from the MOSFET switches. This results in lower switching loss when the circuit is operated from high AC line voltages (220 VAC). With high ac-line voltage the UCC28061 usually doesn’t e sufficient on-time demanded to engage pha ‘B’ of the circuit.
The PWMCNTL pin (pin 9) of the UCC28061 provides an automatic on/off enable for a downstream converter. This is ud to prevent the LLC ries-resonant converter from starting up before the output voltage from the PFC pre-regulator has reached a minimum value. The output voltage is nd through a resistor divider connected at the VSENS pin (pin 2). The on/off threshold and hysteresis are controlled by the gain and output impedance of the divider. The values lected for this design provide a nominal ‘on’ threshold of 330 VDC, and an ‘off’ threshold of 300 VDC for the resonant converter.
4.2 LLC Series-Resonant DC-DC Converter
The LLC ries-resonant DC-DC converter is powered from the regulated output of the boost PFC pre-regulator. The circuit compris of a ½-bridge power stage, which is connected to the ries elements of an LLC resonant circuit. The resonant circuit is formed by the ries combination of a low-value resonant inductance, the magnetizing inductance of the main transformer, and combined capacitance on the passive side of the bridge. The resonant frequency is t by resonant inductance (17.5 µH‡) and circuit capacitance (0.045 µF). The values t the resonant frequency of this circuit to between 175 kHz and 180 kHz.
When operated at the resonant frequency, the voltages across the resonant components of the circuit cancel, allowing the full peak-peak voltage from the power stage to be applied across the transformer primary. This is the unity gain operating condition. By then varying the stimulus frequency either below or above resonance, the gain of the circuit, and hence the output voltage, can be incread or decread respectively. The switch frequency of the power stage is the control parameter that regulates the output of a resonant converter.
In this design the main transformer and resonant inductor are reprented by parate components. Commercial designs often integrate the resonant inductor into the transformer as the leakage component. This is fairly easy to achieve when a traditional ferrite ‘E’ core is ud for the main transformer. In order to meet the low-profile requirement of this design, planar magnetic components were lected. Integrating the resonant inductance into the main transformer is more difficult to achieve with a planar transformer. In particular, power dissipation is significantly incread. However the availability of new ferrite geometries may make it possible to achieve a low-profile design using a traditional E-core shape.
The magnetizing inductance of the main transformer affects the gain variation of the circuit versus the switching frequency. It also plays an important role in limiting the switching loss of the MOSFE
T drivers. Energy stored in the magnetizing inductance caus current to circulate during the short period when both MOSFET switches are ‘off’. The pha of this current has the effect of reducing the voltage across the next MOSFET to be turned on. This is referred to as zero-voltage switching (ZVS). It improves efficiency by significantly reducing the switching loss of the converter. It also reduces the magnitude of electrical noi generated by the circuit compared to a more rapid collap of the MOSFET drain voltage with normal switching.
The ½-bridge power stage operates at 50% duty and varying frequency. The upper and lower MOSFETs of the bridge are controlled by the UCC25600 IC via an isolated gate drive. The converter output voltage is regulated by a TL431A shunt regulator located in the condary. The error signal generated from the TL431A is pasd back to the converter primary using an opto’ coupler. A decrea in the error voltage at the output of the opto’ coupler increas the current pulled from RC pin (pin 2) of the UCC25600. This increas the switching frequency of the converter, which reduces its gain and output voltage.
‡ Includes the primary referred leakage inductance of the main transformer
The UCC25600 is a very simple and low-cost part to u. In addition to providing a variable drive fre
quency for ½-bridge power stage, it includes a soft-start feature, over-current shutdown protection, and adjustment of MOSFET switch dead time.
The circuit ns load current through the resonant capacitance using a parallel 0.001-µF capacitor as an impedance divider. Current through this capacitor is half-wave rectified and then pasd through a low-value n resistor. The resulting signal is then filtered and fed to the OC pin (pin 3) of the UCC25600. Our testing suggests that this method of nsing current results in less variation of the nd current with switching frequency.
The resonant current is susceptible to a high surge current during converter start-up. For this reason it is recommended that the nsitivity of the current n is reduced during converter start up. In the reference circuit this is accomplished with a P-channel JFET and a divider resistor. The gate of the JFET is connected to the SS pin (pin 4) of the UCC25600, which is initially low during converter start up. The JFET places the divider resistor in circuit during the period that its gate voltage is low. When the soft start period is complete the JFET turns off to return current nsitivity to normal.
Other protection features, such as over-voltage shutdown, are easily implemented by momentarily pulling the SS pin (pin 4) of the UCC25600 to ground. Over-voltage protection has been added to th
e reference design using this method. At the converter output a 27-V Zener diode is ud to n an output over voltage. The diode is connected in ries with an opto’ coupler. When the output voltage is sufficiently high to break down the Zener diode, the output of the coupler pulls down the soft-start pin to the UCC25600.
A limitation of LLC ries-resonant converters is that they operate over a limited input voltage range. This is becau below a certain operating frequency the frequency-gain relationship of the converter is reverd. The operating frequency of the UCC25600 is controlled by the magnitude of current flowing from the RT pin (pin 2). A resistor to ground, R309, ts the minimum operating frequency to approximately 110 kHz.
To limit the surge current during start up the UCC25600 incorporates a soft-start feature. During the soft-start period the control frequency is pushed 100 kHz above the minimum frequency t by R309. For some designs the frequency may still not be high enough to limit the surge current in the ries-resonant circuit. For this reason the components C323 and R324 are added so make the resistance, from the RT pin to ground, appear initially lower. This effect lasts for only the few milli-conds it takes for C323 to charge.
An automatic on/off enable signal (CONV_OFF) prevents the resonant converter starting until there is sufficient voltage output from the upstream PFC pre-regulator. This signal is ud to hold down the SS pin (pin 4) whenever the output voltage from the PFC stage is insufficient for the resonant converter to produce a regulated output. In this ca a simple NPN bipolar transistor is ud to ground the SS pin whenever the CONV_OFF control signal is high.
4.3 5-W Bias Converter
The 5-W bias supply is produced by a simple flyback converter. This regulator provides 15-VDC bias to power the control circuits on the primary side of the power supply. The circuit is bad on the UCC2813D-4, a small current-mode controller. The converter is powered from the output of the PFC pre-regulator stage and must be able to start up prior to the PFC stage being operational. For this reason the circuit is designed to operate over a wide input voltage, 100 – 450 VDC. The low power level and current limit tting of this circuit eliminates the need for a snubber at the MOSFET drain. It also ensures that the flyback transformer is confined to operating in discontinuous current mode (DCM).
For applications that have higher bias power requirements, or require a significant amount of standb
y power in the condary, a converter design bad on the UCC28610 is recommended. The UCC28610 is a robust and efficient controller that is capable of meeting the high efficiency and low standby power limitations demanded by EnergyStar®.
4.4 PCB Jumper Settings
The PCB design includes two 0.1-in spaced pin headers, J3 and J6. Using standard shorting jumpers, the headers provide on/off and power-up options for the board for diagnostic purpos. The jumper ttings are described as follows.
