SPI Interfaces
Table 43:SPI Master Mode Interface Switching Characteristics (1)在线日语学习
赫尔辛基大学
Symbol Description
Min Typ Max Units T DCMSPICLK SPI master mode clock duty cycle –50–%T MSPIDCK Input tup time for SPI {0,1}_MISO 2.00––ns T MSPICKD Input hold time for SPI {0,1}_MISO
8.20––ns T MSPICKO Output delay for SPI {0,1}_MOSI and SPI {0,1}_SS –3.10– 3.90ns
T MSPISSCLK Slave lect asrted to first active clock edge 1––F SPI_REF_CLK cycles T MSPICLKSS Last active clock edge to slave lect deasrted 0.5––F SPI_REF_CLK cycles
gpiF MSPICLK SPI master mode device clock frequency ––50.00MHz F SPI_REF_CLK SPI reference clock frequency
–
–
200.00
MHz
Notes:
调整心态1.
Test conditions: LVCMOS33, slow slew rate, 8mA drive strength, 15pF loads.
Figure 12:SPI Master (CPHA =0) Interface Timing Diagram
Figure 13:SPI Master (CPHA =1) Interface Timing Diagram
PL Performance Characteristics
This ction provides the performance characteristics of some common functions and designs implemented in the PL. The numbers reported here are worst-ca values; they have all been fully characterized. The values are subject to the same guidelines as the AC Switching Characteristics, page 15. In each table, the I/O bank type is either High Performance (HP) or High Range (HR).
Table 53 provides the maximum data rates for applicable memory standards using the Zynq-7000SoC memory PHY. The final performance of the memory interface is determined through a complete design implemented in the Vivado or ISE Design Suite, following guidelines in the Zynq-7000 SoC and 7Series Devices Memory Interface Solutions Ur Guide (UG586).
Table 52:PL Networking Applications Interface Performances
Description
I/O Bank Type Speed Grade
Units -3E -2E/-2I/-2LI
-
carryover1C/-1I -1Q/-1LQ SDR LVDS transmitter (using OSERDES; DATA_WIDTH =4 to 8)HR 710710625625Mb/s HP 710710625625Mb/s DDR LVDS transmitter (using OSERDES; DATA_WIDTH =4 to 14)HR 12501250950950Mb/s HP 1600140012501250Mb/s SDR LVDS receiver (SFI-4.1)(1)HR 710710625625Mb/s HP 710710625625Mb/s DDR LVDS receiver (SPI-4.2)(1)
HR 12501250950950Mb/s HP
1600
1400
1250
1250
Mb/s
nutritionistNotes:
1.
LVDS receivers are typically bounded with certain applications where specific dynamic pha-alignment (DPA) algorithms dominate deterministic performance.
PS Configuration
DDR Memory Interfaces
Table 25:PS Ret/Power Supply Timing Requirements
Symbol Description
PS_CLK Frequency
(MHz)
Min Max Units T SLW (1)
冬季连衣裙搭配吕布与貂蝉的故事128KB CRC eFUSE disabled and PLL enabled.Default configuration
301239ms 33.331240ms 601340ms 128KB CRC eFUSE disabled and PLL in bypass.
30–3213ms 33.33–2713ms 60
–925ms 128KB CRC eFUSE enabled and PLL enabled.(2)
30–199ms 33.33–1612ms 60
–325ms 128KB CRC eFUSE enabled and PLL in bypass.(2)
30–830–788ms 33.33–746–705ms 60
–408
–374
ms
Notes:
1.Valid for power supply ramp times of less than 6ms. For ramp times longer than 6ms, e the BootROM Performance ction of the Zynq-7000SoC Technical Reference Manual (UG585).
2.
If any PS and PL power supplies are tied together, obrve the PS_POR_B asrtion time requirement (T PSPOR ) in Table 24 and its accompanying note.
Table 26:Processor Configuration Access Port Switching Characteristics
Symbol Description
Min Typ Max Units F PCAPCK
Maximum processor configuration access port (PCAP) frequency
–
–
100
MHzunfccc
Table 27:DDR3 Interface Switching Characteristics (1333Mb/s)(1)
Symbol Description Min Max Units T DQVALID (2)Input data valid window 450–ps T DQDS (3)Output DQ to DQS skew 95–ps T DQDH (4)Output DQS to DQ skew 222–ps T DQSS Output clock to DQS skew
–0.110.08T CK T CACK (5)Command/address output tup time with respect to CLK 465–ps T CKCA (6)
Command/address output hold time with respect to CLK
528
–
ps
质量等级领域：宇航级IC 、特军级IC 、超军级IC 、普军级IC 、禁运IC 、工业级IC ，军级二三极管，功率管等;
应用领域：航空航天、船舶、汽车电子、军用计算机、铁路、医疗电子、通信网络、电力工业以及大型工业设备
祝您：工作顺利，生活愉快!
以深圳市美光存储技术有限公司提供的参数为例，以下为XC7Z035-2FFG676I的详细参数，仅供参考
come across
