The Alternate Arm Converter:A New
Hybrid Multilevel Converter With DC-Fault
Blocking Capability
Michaël M.C.Merlin,Member,IEEE,Tim C.Green,Senior Member,IEEE,
Paul D.Mitcheson,Senior Member,IEEE,David R.Trainer,Roger Critchley,Will Crookes,and Fainan Hassan
Abstract—This paper explains the working principles,sup-ported by simulation results,of a new converter topology intended for HVDC applications,called the alternate arm converter(AAC). It is a hybrid between the modular multilevel converter,becau of the prence of H-bridge cells,and the two-level converter,in the form of director switches in each arm.This converter is able to generate a multilevel ac voltage and since its stacks of cells consist of H-bridge cells instead of half-bridge cells,they are able to gen-erate higher ac voltage than the dc terminal voltage.This allows the AAC to operate at an optimal point,called the“sweet spot,”where the ac and dc energyflows equal.The director switches in the AAC are responsible for alternating the conduction period of each arm,leadin
g to a significant reduction in the number of cells in the stacks.Furthermore,the AAC can keep control of the current in the pha reactor even in ca of a dc-side fault and support the ac grid,through a STATCOM mode.Simulation results and loss calculations are prented in this paper in order to support the claimed features of the AAC.
wellbeingIndex Terms—AC–DC power converters,emerging topologies, fault tolerance,HVDC transmission,multilevel converters,power system faults,STATCOM.
I.I NTRODUCTION
I NCREASING attention is being paid to HVDC transmis-
sion systems,especially becau most of the new schemes are intended to connect remote renewable sources to the grid and the most effective way to do it is to transmit the generated power using HVDC instead of HV AC[1].For offshore HVDC applica-tions,voltage-source converters(VSCs)are more suitable than current-source converters(CSCs)[2]due to to their black-start capability and ability to operate in weak ac grids,such as a net-work of wind turbine generators.However,compared to CSCs, their power ratings are limited and their efficiency is somewhat国王的演讲英文字幕
Manuscript received August27,2012;revid May22,2013and August09, 2013;accepted September04,2013.Date of publication October07,2013;date of current version January21,2014.This work was supported in part by the Supergen FlexNet Rearch Consortium(ESPRC Grant EP/E04011X/1)and in part by Alstom Grid.Paper no.TPWRD-00896-2012.
M.M.C.Merlin,T.C.Green,and P.D.Mitcheson are with the Department of Electrical and Electronics Engineering,Imperial College,London SW7 2AZ,U.K.(lin@ic.ac.@ic.ac.uk;paul.mitch-eson@ic.ac.uk).
化妆的基本步骤D.R.Trainer,R.Critchley,R.W.Crookes,and F.Hassan are with Al-stom Grid,Stafford ST174LX,U.K.(; ;).
Color versions of one or more of thefigures in this paper are available online at ieeexplore.ieee.
Digital Object Identifier10.1109/TPWRD.2013.2282171poorer although recent developments in miconductor devices are closing the gap in both cas so that VSCs are becoming economically viable as technological solutions in large HVDC schemes;some of them[3],[4]to be commissioned in the next couple of years.
Since the1990s,a great deal of rearch effort has been directed to improving converters primarily to make them more power efficient than thefirst generation of VSCs[5]–[8]. The modular multilevel converter(MMC),published in1998 for STATCOM applications[9],published in2003for HVDC Power Transmission[10],and followed up in[11]–[13],brought veral new features to VSC.It replaced the ries-connected insulated-gate biploar transistor(IGBT)in each arm of the two-level converter by a stack of half-bridge cells which con-sist of a charged capacitor and a t of IGBTs.Sincet the voltage of each cell is small compared to the ac and dc voltages,a large number of cells are placed in ries in each stack,resulting in the creation of a voltage waveform with numerous steps.This characteristic has two main conquences:1)the generated ac current is very clo to a sine wave and no longer requires any filtering,thus saving the implementation of bulky and costly acfilters and2)the converter does not rely on high-frequency PWM to synthes voltage waveforms,thus greatly reducing the switching loss and thereby improving the overall efficiency of the converter.
Notwithstanding the advantages brought by this new gener-ation of converters,there are some aspects that can still be im-proved.The avoidance of the acfilter means that the cells are now one of the bulkiest components of the converter station and cell format requires a physically large capacitor in addition to the t of IGBTs.Half-bridge cells are normally ud in pref-erence to H-bridge cells(bot
h illustrated in Fig.1)in order to reduce the number of devices in conduction at any time and, therefore,reduce the conduction power loss.Even if this choice is justified by the large cost associated with the power loss,it also means that the converter is vulnerable to a dc-side fault in a similar way to a two-level converter whereas an H-bridge ver-sion would not be.The inability of half-bridge cells to produce a negative voltage results in the conduction of the antiparallel diodes connected to the IGBTs,thus creating an uncontrollable current path in ca of a collap of the dc bus voltage.Since the dc breakers for high-power applications are still under de-velopment[14],[15],the lack of other fast protective mecha-nisms[16]makes this loss of a means to control dc fault current problematic.In[17],the double-clamped submodule(DCS)was
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Fig.1.Electrical schematic of half-bridge cells(left)and H-bridge cells(right). suggested as a new type of cell to deal with this issue.The DCS connects two half-bridge cells together into one cell through one additional IGBT and two diodes.This configuration offers the possibility of switching in a rever voltage,similar to the H-bridge cell,in order to respond to the need for negative stack voltage in ca of a dc-side fault.However the DCS does not fully solve the dc fault issue becau:1)only half the available positive voltage can be translated into negative voltage,leaving
make it bettera voltage deficit from that needed to fully control the current and
2)the power loss are incread by50%compared to using two half-bridge cells during normal operation becau of the addi-tional IGBT in the conduction path.
This paper prents the analysis of a new converter topology, which is part of a new generation of VSCs[18],[19],bad on the multilevel approach but also takes some characteristics from the two-level VSC.As explained through this paper,one of the features of this topology lies in its ability to retain control of the pha current during the loss of the dc-bus voltage,thanks to the prence of H-bridge cells in the arms.The key advantage of this new topology lies in its reduced number of cells;thus, it does not compromi the efficiency of the converter,nor on the number of devices and e
ven saves volume becau of the reduced number of cells per arm.A component level simulation of a20-MW converter is ud to confirm the claimed character-istics of this new topology.
II.D ESCRIPTION OF THE T OPOLOGY
A.Basic Operation
Briefly prented in[20],the alternate arm converter(AAC) is a hybrid topology which combines features of the two-level and multilevel converter topologies.As illustrated in Fig.2, each pha of the converter consists of two arms,each with a stack of H-bridge cells,a director switch,and a small arm in-ductor.The stack of cells is responsible for the multistep voltage generation,as in a multilevel converter.Since H-bridge cells are ud,the voltage produced by the stack can be either positive or negative;thus,the converter is able to push its ac voltage higher than the dc terminal voltage if required.The director switch is compod of IGBTs connected in ries in order to withstand the maximum voltage which could be applied across the director switch when it is in the open state.The main role of this
director Fig.2.Schematic of the alternate arm converter,with the optional middle-point connection shown in a dashed
line.
Fig.3.Idealized voltage and current waveforms over one cycle in a pha con-verter of the AAC,showing the working period of each arm.
switch is to determine which arm is ud to conduct the ac cur-rent.Indeed,the key feature of this topology is to u esntially one arm per half cycle to produce the ac voltage.By using the upper arm to construct the positive half-cycle of the ac sine wave and the lower arm for the negative part,the maximum voltage that each stack of cells has to produce is equal to half of the dc bus voltage,which is approximately half the rating of the arm of the MMC.The resulting voltage and current waveforms of the cells and reactor switches are illustrated in Fig.3.The aim of the AAC is to reduce the number of cells,hence the volume and loss of the converter station.
The short period of time when one armfinishes its working period and hands over conduction of the pha current to the op-posite arm is called the overlap period.Since each arm has an ac-tive stack of cells,it can fully control the arm current to zero be-fore opening the director switch,hence achieving soft-switching
Fig.4.STATCOM modes of the AAC during a dc-side fault:alternate arms (mode A),single working arm(mode B),and dual working arms(mode C). of the director switch,further lowering the power loss.Al-though normally short,the overlap period can provide additional control features,such as controlling the amount of energy stored in the stacks,as explained in Section II-C.
B.DC Fault Management
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One of the important characteristics of this converter is the ability of its arms to produce negative voltage.In fact,the AAC already us this ability to produce a converter voltage higher than the dc terminal voltage without requiring the opposite arm to also produce a higher than normal positive voltage from its stack of cells,provided that the director switch is suitably rated. This ability is put to u in normal operation when the converter produces a voltage which is higher than the dc bus voltage.It can be extended to the ca when the dc bus voltage collaps to a low level,for example,a fault on the dc side.Since enough cells are prent in the stacks to oppo the ac grid voltage,the converter is thus able to keep all of its internal currents under control,in contrast to the two-level converter or half-bridge ver-sion of the MMC.Furthermore,even if the abnce of a dc bus voltage means that it is no longer possible to export ac-tive power to the dc side,it does not prevent reactive power exchange with the ac side.Since the arms of the AAC are still operational,the entire converter can now act as a STATCOM, similar to that in[9].There are some choices over how the di-rector switches are ud in this mode,as illustrated in Fig.4, which lead to different modes that can be achieved by the AAC during a dc-side fault:one arm conducts per half cycle simi-larly to normal operation,one arm works continuously or the two arms working together,potentially increasing the reactive power capability to2.0p.u.This STATCOM mode of managing the converter during dc fault can help to support the ac grid during a dc outage,in contrast to the worning effect that can be brought about by other topologies becau of their inability to control dc-side fault current.
C.Energy Balance
The ability of the converter to generate relativelyfine voltage steps comes from its cells and,more specifically,from the charged capacitors inside.However,since the resulting ac current isflowing through them,the charge of the capacitors willfluctuate over time,depending on the direction of the current and the switching states of the cells.Due to the large number of cells,it is easier to look at the amount of energy which is stored by the stacks of cells as a whole.Assuming that this charge is evenly distributed among the various cells, thanks to some rotation mechanisms,the only requirement left to ensure satisfactory operation of the converter is to keep the energy of the stacks clo to their nominal value.To achieve this,the converter has to be operated in such way that the net energy exchange for the stacks over each half cycle is strictly zero.
Bad on the time functions(1)of and
(1) The energy exchange corresponds to the difference between the amount of energy coming from the ac side(2)and going to the dc side(3)
(2)
(3) By equating the two energies,an ideal operating point is identified as described in(4).This operating point is called the “sweet spot”and is defined by a ratio of the ac voltage magni-tude to dc voltage magnitude
(4) It is important to remark that this sweet spot specifies an ac peak voltage higher than the dc terminal voltage,that is,half the dc bus voltage.The converter is thus required to generate its ac voltage in overmodulation mode,at a level of approximately 27%higher than the dc terminal voltage. The prence of H-bridge cells is thus fully justified since the cells are required to provide a negative voltage,thus pushing the voltage higher than the dc terminal voltage.By choosing the turns ratio of the transformer between the converter and the ac grid in order to obtain the ac voltage of the sweet spot,the con-verted energy willflow through the converter without a deficit or surplus being exchanged with the stacks.
In practice,discrepancies between the converter and its the-oretical model[ud to derived(2)and(3)leading to(4)]will lead to a small fraction of the converted energy being exchanged with the stack.To remedy this,the overlap ,the small period of time when one arm hands over conduction of the pha current to the other arm)can be ud to run a small dc current through both arms to the dc side.This will result in an exchange of energy between the stacks and the dc cap
acitor,which can be ud to balance the energy in the stacks.
quieterthereareD.Number of Devices
The device count in the AAC can be obtained by following a ries of steps,given the particular operating mechanism described before.The calculation prented below only gives the minimal requirement under normal operation.An additional margin has to be added to comply with the different operating conditions applied to each project.It is,however,important to note that the stacks of the AAC can generate as much negative voltage as positive voltage;thus,the AAC is able to provide an ac voltage up to200%of the dc terminal voltage without requiring extra cells.
First,the number of cells is obtained by calculating the max-imum voltage that a stack has to produce.Since the two arms of a single-pha converter have to support at least the total dc bus voltage,and assuming a symmetrical construction,this maximum voltage has to be at least half the dc bus voltage.Fur-thermore,given that this topology is intended to have dc-fault blocking capability,the arms should be able to produce at least the ac peak voltage in order to maintain control over the current in the pha reactor with the dc voltage reduced to zero.There-fore,the stacks should be rated to deliver the ac peak voltage. Since the sweet spot defines the ac peak volta
ge as27%higher than half the dc bus voltage,the minimum requirement can then be incread up to the ac peak voltage.However,if dc-fault blocking is not a requirement,this voltage can remain at half the dc bus voltage.Furthermore,the maximum voltage of the stacks also defines how long an arm can stay active beyond the zero-crossing point of the converter voltage in order to provide an overlap period.The longer the overlap period,the higher the voltage that the stack has to produce,hence the more cells are required.Once the maximum voltage of the stack is t,the number of cells is directly obtained by dividing this voltage by the nominal voltage of a cell.
Second,the required number of ries IGBTs,which form the director switch,is determined bad on the maximum voltage applied across the director switch,as illustrated in Fig.3.This voltage is the difference between the converter voltage and the voltage at the other end of the director switch,which is con-nected to the(nonconducting)stack of cells.The nonconducting stack can be t to maximize its voltage in order to lower the voltage across the director switch,taking care not to rever the voltage across the director switch.Equation(5)summarizes all of the arguments and prents the maximum voltage across the director switch.By implementing the sweet spot definition (4)into(5),it yields(6),a function of the dc bus voltage and the peak stack voltage
(5)
(6) Table I summarizes the voltage ratings required of the stack of cells and the director switch given three choices made over the need to block dc fault current and the extent of overlap.In defining the voltages,the choices will also determine the number of miconductor devices in the AAC.
TABLE I
V OLTAGE R ATINGS OF THE S TACKS AND D IRECTOR S
WITCHES
The resulting number of cells per stack is given by(7),where is the nominal voltage of a cell
(7) Equation(8)prents the total number of miconductor de-vices()in a three-pha AAC,with being the number ries-IGBTs in the director switch obtained by dividing the maximum voltage of a director switch()by the voltage applied to an IGBT,here assumed to be the same to the voltage of a cell().
(8)
Using the dc-fault blocking ca(given in Table I)and the definition of the sweet spot(4),the total number of micon-ductor devices becomes the value of the following equation:
(9)
III.S IMULATION R ESULTS
A.Model Characteristics
In order to confirm the operation of this new topology,a sim-ulation model has been realid in Matlab/Simulink using the SimPowerSystems toolbox.The characteristics of this model have been chon in order to reflect a realistic power system, albeit at medium voltage(MV),and key parameters are sum-marized in Table II.The transformer interfacing the ac grid and the converter ha
s its turns ratio defined such that the con-verter operates clo to the sweet-spot ac voltage,as defined in Section II-C.The number of cells chon for each stack follows the cond ca from Table II so that dc-side fault blocking is available.A small additional allowance was made so that the converter can still operate and block faults with an ac voltage of1.05p.u.The choice is therefore for nine cells charged at1.5 kV each per stack.The minimum number of cells for operation without overlap(sweet spot operation only)and without fault blocking would be ven cells.The choice of nine cells per stack allows the AAC to operate with1-ms overlap period which is sufficient to internally manage the energy storage within the cur-rent rating of the IGBTs(1.2kA).Finally,a dcfilter has been fitted to the AAC model,as illustrated in Fig.2,and tuned to have critical damping and a cutoff frequency at50Hz;well below thefirst frequency component expected on the dc side which is a six-pul ,300Hz in this model).
TABLE II
C HARACTERISTICS OF THE 20-MW AAC M
ODEL
B.Performance Under Normal Conditions
Bad on this model,the behavior of the AAC was simulated under normal conditions in order to test its performance.In this ction,the converter is running in recti fier mode,converting 20MW and providing 5-MV Ar capacitive reactive power.Fig.5shows the waveforms generated by the AAC in this simulation.First,the converter is very responsive.Second,the waveform of the pha current in the ac
grid connection is high quality with only very low amplitude harmonics,as shown by the Fourier analysis in Fig.6.Third,the dc current exhibits the character-istic six-pul ripple inherent in the recti fication method of this converter,but attenuated by an inductor placed between the con-verter and the dc grid.Fourth,this recti fication action of the cur-rent is particularly obrvable in the fourth graph which shows the arm currents in pha A,indicating when an arm is con-ducting.Finally,the fifth graph prents the average voltage of the cells in both stacks of pha A,with their offstate voltage being controlled to stay at the reference value of 1.5kV.
The voltage and current waveforms have been postprocesd together with the switching commands nt to the converter from the controller,in order to determine the generated power loss.For this example,all of the miconductor devices were bad on the same IGBT device [21]from which the loss curves have been extracted to compute the energy lost through conduction and switching at every simulation time step (2s).A simulation of 1.5s was ud in which the first 0.5s was ignored in order to focus only on the steady-state portion.The obtained results are summarized in Table III.
As can be obrved in Table III,the switching loss relative to the total power loss is low,as could be expected from a mul-tilevel converter,meaning that the conduction loss is
沪江网校登录dominant.
Fig.5.Simulation results of a 20-MW AAC model running in recti fier mode under normal
fly walking
conditions.
Fig.6.Fourier transform of the grid-side ac current generated by the AAC.
However,the conduction loss is kept small despite the u of H-bridge cells by the fact that the stacks do not have to be rated for the full dc bus voltage becau of the prence of the di-rector switches;the conduction loss of a director switch device is less than that of an H-bridge cell.The director switches do not incur any switching loss thanks to the soft-switching capability of the arms (through controlling the arm current to zero before opening of the director switch).Finally,a large amount of the power loss comes from the dc inductor but this is not repre-ntative of a large converter.In this scale model of 20MW,the current at 1kA is typical of a much later converter and it is the voltage that has been scalded down by reducing the number of cells and levels (while keeping the cell voltage at a value typical
