`define MUL_MUL 2'b00
`define MUL_SEL_HIGH 'b1
`define MUL_SEL_LOW 'b0
module mul(MUL_Flag,Ret,MUL_DA,MUL_DB,Clk,MUL_DC,MUL_SelHL,MUL_Start,MUL_SelMD,MUL_Write);
input Clk;
input Ret;
兰迪少儿英语input MUL_Start;
input MUL_SelHL;
input [1:0] MUL_SelMD;
input MUL_Write;
output MUL_Flag;
input [31:0] MUL_DB;
input [31:0] MUL_DA;
output [31:0] MUL_DC;
reg [31:0] hi;
reg [31:0] lo;
reg working;
reg [63:0] result;nupt
reg finish;辛辛那提大学排名
ajarreg finish2;
function [63:0] result_mul;
input [31:0] a,b;
begin
result_mul=a*b;
end
endfunction
function [63:0] result_div;
input [31:0] a,b;dockers
begin
result_div[31:0]=a/b;
result_div[63:32]=a%b;
end
苍耳的拼音endfunction
/
/main
assign MUL_Flag=finish;
对接英文assign MUL_DC=finish?(MUL_SelHL==(`MUL_SEL_HIGH)?hi:lo):32'b0;
//assign MUL_DC=finish?(MUL_SelHL?hi:lo):32'b0;
always @(podge Clk)
begin
if(Ret)
begin
working<=1'b0;
finish<=1'b0;
end
el if(MUL_Start)
begin
血亲相奸
finish<=1'b0;
working<=1'b1;
if(MUL_SelMD==2'b00) result<=result_mul(MUL_DA,MUL_DB);
el if(MUL_SelMD==2'b11) result<=result_div(MUL_DA,MUL_DB);
finish<=1'b1;
working<=1'b0;
end
end
//write HI and LO register
always @(podge Clk)
begin
if(Ret)
begin
头衔的意思hi<=32'b0;
lo<=32'b0;
end
el if(MUL_Write)
begin
if(MUL_SelHL==`MUL_SEL_HIGH)
hi<=MUL_DB;
brood
el
lo<=MUL_DB;
end
el if(finish)
begin
hi<=result[63:32];
lo<=result[31:0];
end
end
endmodule
