vivado中遇到的错误
音信（1）
报错：
2013年6月英语四级作文>英语翻译网站[Place 30-574] Poor placement for routing between an IO pin and BUFG. If this sub optimal condition is acceptable for this design, you may u the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the u of this override is highly discouraged. The examples can be ud directly in the .xdc file to override this clock rule.
< t_property CLOCK_DEDICATED_ROUTE FALSE [get_nets ret_IBUF] >
ret_IBUF_inst (IBUF.O) is locked to IOB_X1Y66
and ret_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0
cyan[Place 30-99] Placer failed with error: 'IO Clock Placer failed'
brightcovePlea review all ERROR, CRITICAL WARNING, and WARNING messages during placement to understand the cau for failure.
[Common 17-69] Command failed: Placer could not place all instances
问题段：
reg point = 1'b1 ;
smg U3(.clock(clock),.num(num),.point(point),.lect(sw[3]),.cm(sw[2]),.CX(out_smgC));
always @ ( ret )考研准考证号忘了怎么查询
employee>114schoolbegin
if( ret )
point = ~point;btt
el
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end
这种问题是因为：
从外部来的（接到板⼦上的）always语句中的敏感信号为时钟以外的外部信号，因为Vivado在处理外部时钟信号的时候会⾃动添加BUFG 模块来去除时钟的抖动，但是其他的信号就不会这样做，这样的话在always语句的敏感信号列表中使⽤没有去抖动的外部信号就有可能导致系统不稳定，所以会出现这个错误。
