SCANSTA112
7-port Multidrop IEEE 1149.1(JTAG)Multiplexer
录取通知书英语General Description
The SCANSTA112extends the IEEE Std.1149.1test bus into a multidrop test bus environment.The advantage of a multidrop approach over a single rial scan chain is im-proved test throughput and the ability to remove a board from the system and retain test access to the remaining modules.Each SCANSTA112supports up to 7local IEEE1149.1scan chains which can be accesd individually or combined rially.
Addressing is accomplished by loading the instruction regis-ter with a value matching that of the Slot inputs.Backplane and inter-board testing can easily be accomplished by park-ing the local TAP Controllers in one of the stable TAP Con-troller states via a Park instruction.The 32-bit TCK counter enables built in lf test operations to be performed on one port while other scan chains are simultaneously tested.The STA112has a unique feature in that the backplane port and the LSP0port are bidirectional.They can be configured to alternatively act as the master or slave port so an alternate test master can take control of the entire scan chain network from the LSP0port while the b
ackplane port becomes a slave.
Features
n True IEEE 1149.1hierarchical and multidrop addressable capability
n The 8address inputs support up to 249unique slot address,an Interrogation Address,Broadcast
欺骗英文
Address,and 4Multi-cast Group Address (address 000000is rerved)
n 7IEEE 1149.1-compatible configurable local scan ports n Bi-directional Backplane and LSP 0ports are interchangeable slave ports
n Capable of ignoring TRST of the backplane port when it becomes the slave.
hgfn Stitcher Mode bypass level 1and 2protocols n Mode Register 0allows local TAPs to be bypasd,
lected for inrtion into the scan chain individually,or rially in groups of two or three
n Transparent Mode can be enabled with a single
instruction to conveniently buffer the backplane IEEE 1149.1pins to tho on a single local scan port
n General purpo local port passthrough bits are uful for delivering write puls for Flash programming or monitoring device status.n Known Power-up state
n TRST on all local scan ports n 32-bit TCK counterspeechless什么意思
n 16-bit LFSR Signature Compactor
n Local TAPs can become TRI-STATE via the OE input to allow an alternate test master to take control of the local TAPs (LSP 0-3have a TRI-STATE notification output)n 3.0-3.6V V CC Supply Operation n Supports live inrtion/withdrawal
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temperaturesFIGURE 1.Typical u of SCANSTA112for board-level management of multiple scan chains.
高中物理辅导
May 2004
SCANSTA1127-port Multidrop IEEE 1149.1(JTAG)Multiplexer
©2004National Semiconductor Corporation
Introduction
The SCANSTA112is the third device in a ries that enable multi-drop address and multiplexing of IEEE-1149.1scan chains.The SCANSTA112is a supert of its predecessors -the SCANPSC110and
the SCANSTA111.The STA112has all features and functionality of the two previous devices.The STA112is esntially a support device for the IEEE 1149.1standard.It is primarily ud to partition scan chains into managable sizes,or to isolate specific devices onto a perate chain (Figure 1).The benefits of multiple scan chains are improved fault isolation,faster test times,faster programiing times,and smaller vector ts.
In addition to scan chain partitioning,the device is also addressable for u in a multidrop backplane environment (Figure 2).In this configuration,multiple IEEE-1149.1acces-sible cards with an STA112on board can utilize the same backplane test bus for system-level IEEE-1149.1access.This approach facilitates a system-wide commitment to structural test and programming throughout the entire sys-tem life sycle.
Architecture
Figure 3shows the basic architecture of the ’STA112.The device’s major functional blocks are illustrated here.The TAP Controller,a 16-state state machine,is the central control for the device.The instruction register and various test data registers can be scanned to exerci the various functions of the ’STA112(the registers behave as defined in IEEE Std.1149.1).
The ’STA112lection controller provides the functionality that allows the 1149.1protocol to be ud in a multi-drop environment.It primarily compares the address input to the slot identification and enables the ’STA112for subquent scan operations.
The Local Scan Port Network (LSPN)contains multiplexing logic ud to lect different port configurations.The LSPN control block contains the Local Scan Port Controllers (LSPC)for each Local Scan Port (LSP 0,LSP n ).This control block receives input from the ’STA112instruction register,mode registers,and the TAP controller.Each local port contains all four boundary scan signals needed to inter-face with the local TAPs plus the optional Test Ret signal (TRST).
The TDI/TDO Crossover Master/Slave logic is ud to define the bidirectional B0and B1ports in a Master/Slave configuration.
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FIGURE 2.Example of SCANSTA112in a multidrop addressable backplane.
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SCANSTA112 Array
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FIGURE3.SCANSTA112Block Diagram
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Connection Diagrams
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(BGA Top view)
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SCANSTA112 Connection Diagrams(Continued)
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TQFP pinout
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TABLE 1.Pin Descriptions
Pin Name Description
No.Pins I/O VCC 10N/A Power GND 10N/A Ground
四级听力满分多少分
RESET 1I RESET Input:will force a ret of the device regardless of the current state.ADDMASK 1I ADDRESS MASK input:Allows masking of lower slot input pins.
MPl B1/B01I MASTER PORT SELECTION:Controls lection of LSP B0or LSP B1as the backplane port.The unlected port becomes LSP 00.A value of "0"will lect LSP B0as the master port.SB/S 1I Selects ScanBridge or Stitcher Mode.
LSPl (0-6)
7I In Stitcher Mode the inputs define which LSP’s are to be included in the scan chain TRANS
1
I
Transparent Mode enable input:The value of this pin is loaded into the TRANSENABLE bit of the control register at power-up.This value is ud to control the prence of registers and pad-bits in the scan chain while in the stitcher mode.
TLR_TRST 1I
Sets the driven value of TRST 0-5when LSP TAPs are in TLR and the device is not being ret.During RESET ="0"or TRST B ="0"(IgnoreRet ="0")TRST n ="0".This pin is to be tied low to match the function of the SCANSTA111
TLR_TRST 61I This pin affects TRST of LSP 6only.This pin is to be tied low to match the function of the SCANSTA111
TDI B0,TDI B1
2
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BACKPLANE TEST DATA INPUT:All backplane scan data is supplied to the ’STA112through this input pin.MPl B1/B0determines which port is the master backplane port and which is LSP 00.This input has a 25K Ωinternal pull-up resistor and no ESD clamp diode (ESD is controlled with an alternate method).When the device is power-off (V DD floating),this input appears to be a capacitive load to ground (Note 1).When V DD =0V (i.e.;not
floating but tied to V SS )this input appears to be a capacitive load with the pull-up to ground.TMS B0,TMS B1
2I/O
BACKPLANE TEST MODE SELECT:Controls quencing through the TAP Controller of the ’STA112.Also controls quencing of the TAPs which are on the local scan chains.
MPl B1/B0determines which port is the master backplane port and which is LSP 00.This bidirectional TRISTATE pin has 24mA of drive current,with a 25K Ωinternal pull-up resistor and no ESD clamp diode (ESD is controlled with an alternate method).When the device is power-off (V DD floating),this input appears to be a capacitive load to ground (Note 1).When V DD =0V (i.e.;not floating but tied to V SS )this input appears to be a capacitive load with the pull-up to ground.
TDO B0,TDO B1
2I/O
BACKPLANE TEST DATA OUTPUT:This output drives test data from the ’STA112and the local TAPs,back toward the scan master controller.This bidirectional TRISTATE pin has 12mA of drive current.MPl B1/B0determines which port is the master backplane port and which is LSP 00.Output is sampled during interrogation addressing.When the device is power-off (V DD =0V or floating),this output appears to be a capacitive load (Note 1).TCK B0,TCK B1
2I/O
TEST CLOCK INPUT FROM THE BACKPLANE:This is the master clock signal that controls all scan
operations of the ’STA112and of the local scan ports.MPl B1/B0determines which port is the master backplane port and which is LSP 00.The bidirectional TRISTATE pins have 24mA of drive current with hysterisis.This input has no pull-up resistor and no ESD clamp diode (ESD is controlled with an alternate method).When the device is power-off (V DD floating),this input appears to be a capacitive load to ground (Note 1).When V DD =0V (i.e.;not floating but tied to V SS )this input appears to be a capacitive load to ground.
TRST B0,TRST B1
2I/O
TEST RESET:An asynchronous ret signal (active low)which initializes the ’STA112logic.MPl B1/B0determines which port is the master backplane port and which is LSP 00.This bidirectional TRISTATE pin has 24mA of drive current,with a 25K Ωinternal pull-up resistor and no ESD clamp diode (ESD is controlled with an alternate method).When the device is power-off (V DD floating),this pin appears to be a capacitive load to ground (Note 1).When V DD =0V (i.e.;not floating but tied to V SS )this input appears to be a capacitive load with the pull-up to ground.
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