专利名称：VERIFICATION ITEM EXTRACTION
APPARATUS AND METHOD
jack slow fuck发明人：Motoya Tanigawa,Noriyuki Ikeda,Akiji
contestantsWatanabe,Jun Tanowaki
申请号：US14244483
恋爱时代 李胜基
undermine申请日：20140403
suarez公开号：US20140304669A1doing
yui natsuki公开日：
星期四英文
20141009
专利内容由知识产权出版社提供
专利附图：sheeting
摘要：A verification item extraction apparatus is disclod that performs a priority determination process. Connection relationships pertinent to input/output are derived
for each of logics in a verification subject circuit bad on connection information acquired from description data in a storage part. A first priority for verifying the logics is determined bad on the connection relationships being derived. Related I/Fs, which are related to inputs to the logics and are interfaces to an outside of the verification subject circuit, are extracted bad on the connection information. Second priority for verifying the related I/Fs is determined bad on the first priority.
申请人：FUJITSU SEMICONDUCTOR LIMITED法语学习网
地址：Yokohama-shi JP
国籍：JP
更多信息请下载全文后查看
