专利名称:DUTY CYCLE CORRECTION CIRCUIT
发明人:Tandon, Prakhar,Dubey, Shivesh Kumarrubber的复数
申请号:EP21164150.1
申请日:20210323
公开号:EP3902140A2
公开日:
耐用
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摘要:A duty cycle correction circuit (106) includes a duty cycle adjuster (108) that is configured to receive first and cond differential input signals (D1, D2) having first and cond duty cycles, respectively, that are distorted with respect to a reference duty cycle. The duty cycle adjuster is further configured to iteratively adjust the first and
北大青鸟培训课程cond duty cycles to generate first and cond differential output signals (O1, O2) having third and fourth duty cycles that are within a predefined range of the reference duty cycle, respectively. During each iteration, the duty cycle adjuster adjusts the first and cond duty cycles bad on correction bits (B1-B4) that are generated bad on a duty cycle detection signal (DS) that indicates whether the third duty cycle is greater than or less than the fourth duty cycle, and a lock signal (LOCK) that is activated when the duty cycle detection signal toggles from one logic state to another.
申请人:NXP B.V.
地址:High Tech Campus 60 5656 AG Eindhoven NL
国籍:NL
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代理机构:Hardingham, Christopher Mark
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