Introduction
The Spartan ®-IIE Field-Programmable Gate Array family gives urs high performance, abundant logic resources, and a rich feature t, all at an exceptionally low price. The ven-member family offers densities ranging from 50,000 to 600,000 system gates, as shown in Table 1. System per-formance is supported beyond 200 MHz.
Features include block RAM (to 288K bits), distributed RAM (to 221,184 bits), 19 lectable I/O standards, and four DLLs (Delay-Locked Loops). Fast, predictable interconnect means that successive design iterations continue to meet timing requirements.
The Spartan-IIE family is a superior alternative to
mask-programmed ASICs. The FPGA avoids the initial cost, lengthy development cycles, and inherent risk of conventional ASICs. Also, FPGA programmability permits design upgrades in the field with no hardware replacement necessary (impossible with ASICs).
Features
•
Second generation ASIC replacement technology -Densities as high as 15,552 logic cells with up to
600,000 system gates
-Streamlined features bad on Virtex ®-E FPGA
architecture
队长的英文-Unlimited in-system reprogrammability -Very low cost
-Cost-effective 0.15 micron technology •
System level features
-SelectRAM™ hierarchical memory:
·16 bits/LUT distributed RAM ·Configurable 4K-bit true dual-port block RAM
·
Fast interfaces to external RAM
-
Fully 3.3V PCI compliant to 64 bits at 66 MHz and
CardBus compliant六级题型
-Low-power gmented routing architecture -Dedicated carry logic for high-speed arithmetic -Efficient multiplier support
-Cascade chain for wide-input functions
-Abundant registers/latches with enable, t, ret -Four dedicated DLLs for advanced clock control
·Eliminate clock distribution delay ·Multiply, divide, or pha shift
-Four primary low-skew global clock distribution nets -IEEE 1149.1 compatible boundary scan logic •
Versatile I/O and packaging -Pb-free package options
-Low-cost packages available in all densities
going home-Family footprint compatibility in common packages -19 high-performance interface standards
·LVTTL, LVCMOS, HSTL, SSTL, AGP , CTT, GTL ·LVDS and LVPECL differential I/O
-Up to 205 differential I/O pairs that can be input,
output, or bidirectional
-Hot swap I/O (CompactPCI friendly)
issac
•Core logic powered at 1.8V and I/Os powered at 1.5V ,2.5V , or 3.3V
•
Fully supported by powerful Xilinx ® ISE ® development system
-Fully automatic mapping, placement, and routing -Integrated with design entry and verification tools -Extensive IP library including DSP functions and
soft processors
DS077-1 (v3.0) August 9, 2013
Product Specification
质量等级领域：宇航级IC 、特军级IC 、超军级IC 、普军级IC 、禁运IC 、工业级IC ，军级二三极管，功率管等;
应用领域：航空航天、船舶、汽车电子、军用计算机、铁路、医疗电子、通信网络、电力工业以及大型工业设备
祝您：工作顺利，生活愉快!
以赛灵思半导体（深圳）有限公司提供的参数为例，以下为XC2S30-5VQG100I的详细参数，仅供参考
Spartan-IIE FPGA Family: Introduction and Ordering Information
General Overview
The Spartan-IIE family of FPGAs have a regular, flexible, programmable architecture of Configurable Logic B locks (CLB s), surrounded by a perimeter of programmable Input/Output B locks (IOB s). There are four Delay-Locked Loops (DLLs), one at each corner of the die. Two columns of block RA大学英语听力
M lie on opposite sides of the die, between the CLBs and the IOB columns. The XC2S400E has four col-umns and the XC2S600E has six columns of block RAM. The functional elements are interconnected by a powerful hierarchy of versatile routing channels (e Figure 1). Spartan-IIE FPGAs are customized by loading configura-tion data into internal static memory cells. Unlimited repro-gramming cycles are possible with this approach. Stored values in the cells determine logic functions and intercon-nections implemented in the FPGA. Configuration data can be read from an external rial PROM (master rial mode), or written into the FPGA in slave rial, slave parallel, or B oundary Scan modes. Xilinx offers multiple types of low-cost configuration solutions including the Platform Flash in-system programmable configuration PROMs. Spartan-IIE FPGAs are typically ud in high-volume appli-cations where the versatility of a fast programmable solution adds benefits. Spartan-IIE FPGAs are ideal for shortening product development cycles while offering a cost-effective solution for high volume production. Spartan-IIE FPGAs achieve high-performance, low-cost operation through advanced architecture and miconduc-tor technology. Spartan-IIE devices provide system clock rates beyond 200 MHz. In addition to the conventional ben-efits of high-volume programmable logic solutions, Spar-tan-IIE FPGAs also offer on-chip synchronous single-port and dual-port RAM (block and distributed form), DLL clock drivers, programmable t and ret on all flip-flops, fast carry logic, and many other features.
Spartan-IIE Family Compared to Spartan-II Family
•Higher density and more I/O
•Higher performance
make的用法•Unique pinouts in cost-effective packages •Differential signaling
inpractice
鄙视你的英文-LVDS, Bus LVDS, LVPECL
•V CCINT = 1.8V
-Lower power
-5V tolerance with external resistor
-3V tolerance directly
•PCI, LVTTL, and LVCMOS2 input buffers powered by V CCO instead of V CCINT
•
bookkeeper
Unique larger bitstream
Bit Sequence Array The bit quence within each IOB is: In, Out, 3-State. The
input-only pins contribute only the In bit to the boundary
scan I/O data register, while the output-only pins contributes
all three bits.
From a cavity-up view of the chip (as shown in the FPGA
Editor), starting in the upper right chip corner, the boundary
scan data-register bits are ordered as shown in Figure 15.
B SDL (B oundary Scan Description Language) files for
Spartan-IIE family devices are available on the Xilinx web
site.
Spartan-IIE FPGA boundary scan IDCODE values are
shown in Table 9.
Figure 15: Boundary Scan Bit Sequence
Table 9: Spartan-IIE IDCODE Values
If CCLK is slower than F CCNH, the FPGA will never asrt BUSY. In this ca, the above handshake is unnecessary, and data can simply be entered into the FPGA every CCLK cycle.
A configuration packet does not have to be written in one continuous stretch, rather it can be split into many write quences. Each quence would involve asrtion of CS. In applications where multiple clock cycles may be required to access the configuration data before each byte can be loaded into the Slave Parallel interface, a new byte of data may not be ready for each concutive CCLK edge. In such a ca the CS signal may be deasrted until the next byte is valid on D0-D7. While CS is High, the Slave Parallel inter-face does not expect any data and ignores all CCLK transi-tions. However, to avoid aborting configuration, WRITE must continue to be asrted while CS is asrted during CCLK transitions.
Abort
To abort configuration during a write quence, deasrt WRITE while holding CS Low. The abort operation is initi-ated at the rising edge of CCLK. The device will remain BUSY until the aborted operation is complete. After aborting configuration, data is assumed to be unaligned to word boundaries and the FPGA requires a new synchronization word prior to accepting any new packets.
Boundary-Scan Configuration Mode
In the boundary-scan mode, no nondedicated pins are required, configuration being done entirely through the IEEE 1149.1 T est Access Port (TAP).
Configuration through the TAP us the special CFG_IN instruction. This instruction allows data input on TDI to be converted into data packets for the internal configuration bus.
The following steps are required to configure the FPGA through the boundary-scan port.
1.Load the CFG_IN instruction into the boundary-scan
instruction register (IR)
2.Enter the Shift-DR (SDR) state
3.Shift a standard configuration bitstream into TDI
4.Return to Run-T est-Idle (RTI)
5.Load the JSTART instruction into IR
6.Enter the SDR state
7.Clock TCK (if lected) through the startup quence
(the length is programmable)书到用时方恨少的意思
8.Return to RTI
Configuration and readback via the TAP is always available. The boundary-scan mode simply locks out the other modes. The boundary-scan mode is lected by a <10x> on the mode pins (M0, M1, M2). Note that the PROGRAM pin must be pulled High prior to reconfiguration. A Low on the PRO-GRAM pin rets the TAP controller and no boundary scan operations can be performed. See Xilinx Application Note XAPP188 for more information on boundary-scan configu-ration.
Readback
The configuration data stored in the Spartan-IIE FPGA con-figuration memory can be read back for verification. Along with the configuration data it is possible to read back the contents of all flip-flops/latches, LUT RAMs, and block RAMs. This capability is ud for real-time debugging.
For more detailed information e Xilinx Application Note XAPP176,Configuration and Readb ack of the Spartan-II and Spartan-IIE FPGA Families.
Figure 21: Loading Configuration Data for the Slave
Parallel Mode
