Secondary Side Average Current Mode Controller
UC2826UC3826
FEATURES
•
Practical Secondary Side Control of Isolated Power Supplies
• 1MHz Operation •Tailored Loop Bandwidth Provides
Excellent Noi Immunity •Voltage Feedforward Provides Superior Transient Respon •Accurate Programmable Maximum Duty Cycle
• Multiple Chips Can be Synchronized to Fastest Oscillator
•
Wide Gain Bandwidth Product (70MHz, Acl>10) Current Error Amplifier
•
Up to Ten Devices Can Easily Share a Common Load
DESCRIPTION
The UC1826 family of average current mode controllers accurately accomplishes condary side average current mode control.The c-ondary side output voltage is regulated by nsing the output voltage and differentially nsing the AC switching current.The nd output voltage drives a voltage error amplifier.The AC switching current, mon-itored by a current n resistor, drives a high bandwidth, low offt current error amplifier.The output of the voltage error amplifier can be ud to drive the current amplifier which filters the measured inductor current.Fast transient respon is accomplished by utilizing voltage feedforward in generating the PWM ramp.
The UC1826 features load share, oscillator synchronization, undervolt-age lockout, and programmable output control.Multiple chip operation can be achieved by connecting up to ten UC1826 chips in parallel.The SHARE bus and CLKSYN bus provide load sharing and synchroniza-tion to the fastest oscillator respectively.With its tailored bandwidth, the UC1826 provides excellent noi immunity and is an ideal controller to
achieve high power, condary side average current mode control.
7/95
BLOCK DIAGRAM
九月 英语ABSOLUTE MAXIMUM RATINGS
Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20V Output Current Source or Sink . . . . . . . . . . . . . . . . . . . . . .0.3A Analog Input Voltages . . . . . . . . . . . . . . . . . . . . . . .−0.3V to 7V ILIM, KILL, SEQ, ENBL, RUN, PWRSEN, PWROK . . . .−0.3V to 7V CLKSYN Current Source . . . . . . . . . . . . . . . . . . . . . . . . .20mA RUN Current Sink . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20mA SEQ Current Sink . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20mA RDEAD Current Sink . . . . . . . . . . . . . . . . . . . . . . . . . . . .20mA RAMP Current Sink . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20mA Share Bus Voltage (voltage with respect to GND) . . .0V to 6.2V ADJ Voltage (voltage with respect to GND) . . . . . .0.9V to 6.3V VEE (voltage with respect to GND) . . . . . . . . . . . . . . . . . .−1.5V
PARAMETER TEST CONDITIONS MIN
TYP MAX UNITS Current Error Amplifier Ib 0.5
3µA
Vio T A = +25°C
0.753mV Over Temperature
5
mV Avo 6090dB GBW (Note 2)Acl =10, R IN =1k, CC =15pF , f =200kHz (Note 1)4570MHz Vol I O =1mA, Voltage above VEE 0.5V Voh I O =0mA
3.8V I O =−1mA
3.5V
Voltage Error Amplifier Ib 0.53µA
Vio 5
zippermV Avo 60
90
dB
Storage T emperature . . . . . . . . . . . . . . . . . . . .−65°C to +150°C Junction Temperature . . . . . . . . . . . . . . . . . . .−65°C to +150°C Lead Temperature (Soldering, 10 c.) . . . . . . . . . . . . .+300°C All voltages with respect to VEE except where noted;all currents are positive into, negative out of the specified terminal.
Consult Packaging Section of Databook for thermal limitations and considerations of packages.
RECOMMENDED OPERATING CONDITIONS
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8V to 20V Sink/Source Output Current . . . . . . . . . . . . . . . . . . . . . .250mA Timing Resistor R T . . . . . . . . . . . . . . . . . . . . . . . . . .1k to 200k Timing Capacitor C T . . . . . . . . . . . . . . . . . . . . . . . .75pF to 2nF
CONNECTION DIAGRAMS
ELECTRICAL CHARACTERISTICS Unless otherwi stated the specifications apply for T A =−55°C to +125°C for
UC1826;−40°C to +85°C for UC2826;and 0°C to +70°C for UC3826;VCC =12V , VEE =GND, Output no load, C T =345pF , R T =4k Ω, RDEAD =1000Ω, C RAMP =345pF , R RAMP =35.2k Ω, R CLKSY
N = 1k, T A =T J .
PARAMETER TEST CONDITIONadda
MIN
TYP MAX UNITS
Voltage Error Amplifier (cont.)GBW (Note 2) f =200kHz 7
MHz Vol I O =175mA, Volts above VEE 0.6V Voh ILIM =3V 2.853
3.15V Voh-ILIM Tested ILIM =0.5V , 1.0V , 2.0V −100
100mV 2X Amplifier and Share Amplifier V offt (b;y = mx + b)20mV GAIN (m;y = mx + b)Slope with AV OUT =1V and 2V 1.98
2.02
V GBW (Note 2)100kHZ R SHARE VCC =0, V SHARE /I SHARE 200k ΩTotal Offt Negative supply is VEE, GND Open,VAO = GND −75075mV Vol VAO = Voltage Amp Vol, Volts above VEE 0.
20.450.6V Voh I O =0mA, ILIM =3V , VAO = Voltage Amp Voh世界杯 英文
5.76
6.3V I O =−1mA, ILIM =3V , VAO = Voltage Amp Voh
5.76
6.3V Adjust Amplifier Vio 406080mV gm I O =−2µA to 2µA, C ADJ = 0.1µF −0.1−0.3mS Vol I OUT =0
0.91 1.1V I OUT =2µA
0.851 1.15V Voh I OUT =0, V SHARE =6.5V
5.76
6.3V I OUT =−2µA, V SHARE =6.5V
5.76
6.3V Oscillator Frequency
450500550kHz Max Duty Cycle
727680%OSC Ramp Amplitude 2
2.2 2.4V Ramp Saturation I O =10mA, OSC =0V 0.440.8V Clock Driver/SYNC (CLKSYN)Vol 0.020.2
V Voh
3.6V R CLKSYN = 200Ω
3.5V I SOURCE 25mA R CLKSYN VCC = 0, V CLKSYN /I CLKSYN 10k V THcountermeasure
1.5V VREF Comparator Turn-on Threshold 4.65V Hysteresis
0.4
V VCC Comparator Turn-on Threshold 7.9
8.48.9
V Hysteresis
0.4V PWR Sen Comparator Voltage Threshold 1.25V Vol I O =1mA 0.30.4
V Voh I O =−100µA 4V KILL Comparator Voltage Threshold
3
V
ELECTRICAL CHARACTERISTICS (cont.)Unless otherwi stated the specifications apply for T A =−55°C to
+125°C for UC1826;−40°C to +85°C for UC2826;and 0°C to +70°C for UC3826;VCC =12V , VEE =GND, Output no load, C T =
lacewood345pF , R T =4k Ω, RDEAD =1000Ω, C RAMP =345pF , R RAMP =35.2k Ω, R CLKSYN = 1k, T A =T J .
PARAMETER TEST CONDITION MIN TYP MAX UNITS
Sequence Comparator Voltage Threshold 2.5V SEQ SAT I O =10mA 0.25V Enable Comparator Voltage Threshold 2.5V RUN SAT I O =10mA 0.2V Reference VREF T A =25°C 4.955 5.05V
VCC =15V 4.9 5.1V
Line Regulation 10 < VCC < 20315mV Load Regulation 0 < I O < 10mA 315mV Short Circuit I VREF =0V 306090mA Output Stage Ri Time C L =100pF 1020ns Fall Time C L =100pF 1020ns Voh VCC > 11V , I O =−10mA 8.08.48.8V
I O = −200mA 7.8V
Vol I O = 200mA 3.0V
I O =10mA 0.5V
Virtual Ground V GND − VEE VEE is externally supplied, GND is floating 0.20.75V
and ud as Signal GND.
Icc
Icc (run)2130mA Note 1:Guaranteed by design.Not 100% tested in production.
Note 2:Unless otherwi specified all voltages are with respect to GND.Currents are positive into, ne
gative out of the
specified terminal.
ELECTRICAL CHARACTERISTICS (cont.)Unless otherwi stated the specifications apply for T A =−55°C to
+125°C for UC1826;−40°C to +85°C for UC2826;and 0°C to +70°C for UC3826;VCC =12V , VEE =GND, Output no load, C T =
345pF , R T =4k Ω, RDEAD =1000Ω, C RAMP =345pF , R RAMP =35.2k Ω, R CLKSYN = 1k, T A =T J .
PIN DESCRIPTIONS
ADJ:The output of the transconductance (gm = −0.1mS)amplifier adjusts the control voltage to maintain equal cur-rent sharing.The chip nsing the highest output current will have its output clamped to 1V.A resistor divider between VREF and ADJ drives the control voltage (VA+)for the voltage amplifier.Each slave unit’s ADJ voltage increas (to a maximum of 6V) its control voltage (VA+)until its load current is equal to the master.The 60mV input offt on the gm amplifier guarante
es that the unit nsing the highest load current is chon as the master.The 60mV offt is guaranteed by design to be greater than the inherent offt of the gm amplifier and the buffer amplifier.While the 60mV offt reprents an error in current sharing, the gain of the current and 2X amplifiers reduces it to only 30mV .The total current n gain is
the current amplifier gain.This pin needs a 0.1µF capaci-tor to compensate the amplifier.
CA-,CA+:The inverting and non-inverting inputs to the current error amplifier.This amplifier needs a capacitor between CA- and CAO to t its dominant pole.
CAO:The output of the current error amplifier which is internally clamped to 4V .It is internally connected to the inverting input of the PWM comparator.
CLKSYN:The clock and synchronization pin for the oscillator.This is a bidirectional pin that can be ud to synchronize veral chips to the fastest oscillator.Its input synchronization threshold is 1.4V.The CLKSYN voltage is 3.6V when the oscillator capacitor C T is being discharged, otherwi it is 0V .
ENBL:The active low input with a 2.5V threshold enables the output to switch.SEQ and RUN are driven low when ENBL is above its 2.5V threshold.
GND:The signal ground ud for the voltage n amplifier, current error amplifier, current error amplifier, voltage reference, 2X amplifier, and share amplifier.The output sink transistor is wired directly to this pin.
KILL:The active low input with a 3.0V threshold stops the output from switching.Once this function is activated RUN must be cycled low by driving KILL above 3.0V and either retting the power to the chip (VCC) or retting the ENBL signal.
ILIM:A voltage on this pin programs the voltage error amplifier’s Voh clamp.The voltage error amplifier output reprents the average output current.The Voh clamp con-quently limits the output current.If ILIM is tied to VREF, it defaults to 3.0V.A voltage less than 3.0V connected to ILIM clamps the voltage error amplifier at this voltage and conquently limits the maximum output current.
OSC:The oscillator ramp (not to be confud with PWM ramp) pin has a capacitor C T to ground and two resistors in ries R T and R DEAD to VREF.The total resistance of R T and R DEAD divided by VREF −V OSC ts exponential charge current.The oscillator charges from 1.2V to 3.4V until the output transitions low.At this time an open col-lector transistor is turned on and discharges the C T capacitor through RDEAD.
天津网络培训The charge time is approximately T CHARGE= 2(R T+ R DEAD) ·C T when the R DEAD resistor is ud.
The dead time is approximately T DISCHARGE= 2·R DEAD·C T.
克里斯布朗
1
T CHARGE+ T DISCHARGE
T CHARGE
T CHARGE+ T DISCHARGE
The C T capacitance should be incread by approxi-mately 40pF to account for parasitic capacitance. OUT:The output of the PWM driver.It has an upper clamp of 8.5V.The peak current sink and source are 250mA.All UVLO, SEQ, ENBL, and KILL logic either enable or disable the output driver.
PWRSEN:This pin is the input to the PWROK comparator. PWROK:The output pin from the PWROK comparator.It has a 300µA current source output when driven high. RAMP:An open collector that can
sink 20mA to dis-charge the oscillator capacitor.An RC is tied between VCC and GND to accomplish feedforward.The PWM
output drives this pin.When the output is high, the tran-
sistor is off enabling the charging of the RAMP capacitor.
When the output transitions low, the transistor is turned
on discharging the RAMP capacitor.The voltage at
RAMP ris from 0.2V to near 4V at maximum duty
cycle.Although this is an exponential ramp at high VCC
voltage the ramp appears linear.
RDEAD:The pin that programs the maximum duty cycle
by connecting a resistor between it and OSC.The maxi-
mum duty cycle is decread by increasing this resistor
克里斯布朗value which increas the discharge time.The dead
time, the time when the output is low, is 2 ·R DEAD·C T. The C T capacitance should be incread by approxi-
mately 40pF to account for parasitic capacitance. RUN:This is an open collector logic output that signifies when the chip is operational.RUN is pulled high to VREF through an external resistor when VCC is greater than 8.4V, VREF is greater than 4.65V, SEQ is greater than 2.5V, and KILL lower than 3.0V.RUN connected to the VA+ pin and to a capacitor to ground adds an RC ri time on the VA+ pin initiating a soft start.
SEQ:The quence pin allows the quencing of startup
for multiple units.A resistor between VREF and SEQ and
a capacitor between SEQ and GND create a unique RC
ri time for each unit which quences the output startup. SHARE:The nearly DC voltage reprenting the average output current.This pin is wired directly to all SHARE pins and is the load share bus.
VA-,VA+:The inverting and non-inverting inputs to the
voltage error amplifier.
VAO:The output of the voltage error amplifier.Its Voh is
clamped with the ILIM pin.
VCC:The input voltage to the chip.The chip is opera-
tional between 8.4V and 20V.
VEE:The negative supply voltage to the chip which pow-
ers the lower voltage rail for all amplifiers.The chip is
operational if VEE is connected to GND or if GND is
floating.When voltage is applied externally to VEE, GND
becomes a virtual ground becau of an internal diode
between VEE and GND.The GND current flows through
the forward biad diode and out VEE.GND is always
the signal ground from which the voltage reference and
all amplifier inputs are referenced.
VREF:The reference voltage equal to 5.0V.
男士衣着搭配
(1)Frequency ≈
(2)Maximum Duty Cycle ≈
PIN DESCRIPTIONS (cont.)
