PCI Bus Power Management Interface Specification
Revision 1.0
Draft
Mar. 18, 1997
Revision History
Revision Issue Date Comments
0.99a Feb 13, 1997Formal submission for PCI SIG Ratification
1.0Mar. 18 1997Revision 1.0 Draft Specification
Copyright © 1997, PCI Special Interest Group
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Table of Contents
1. INTRODUCTION (1)
1.1 G OALS OF THIS S PECIFICATION (1)
1.2 T ARGET A UDIENCE (2)
1.3 O VERVIEW / S COPE (3)
1.4 G LOSSARY OF T ERMS (4)
1.5 R ELATED D OCUMENTS (7)精选英文
枯肠
1.6 C ONVENTIONS U SED IN THIS D OCUMENT (7)
2. PCI POWER MANAGEMENT OVERVIEW (8)
2.1 PCI P OWER M ANAGEMENT S TATES (8)
2.1.1 PCI Function Power States (8)
2.1.2 Bus Power States (8)
2.1.3 Device-Class Specifications (8)
2.1.4 Bus Support for PCI Function Power Management (9)
frighten3. PCI POWER MANAGEMENT INTERFACE (11)
3.1 C APABILITIES L IST D ATA S TRUCTURE (12)
3.1.1 Capabilities List Cap_Ptr Location (13)
3.2 P OWER M ANAGEMENT R EGISTER B LOCK D EFINITION (14)
3.2.1 Capability Identifier - Cap_ID (Offt = 0) (14)
3.2.2 Next Item Pointer - Next_Item_Ptr (Offt = 1) (15)
3.2.3 PMC - Power Management Capabilities (Offt = 2) (15)
3.2.4 PMCSR - Power Management Control/Status (Offt = 4) (16)
3.2.5 PMCSR_BSE - PMCSR PCI to PCI Bridge Support Extensions (Offt=6) (19)
3.2.6 Data (Offt = 7) (20)
4. PCI BUS POWER STATES (23)
4.1 PCI B0S TATE - F ULLY O N (24)
4.2 PCI B1S TATE (24)
4.3 PCI B2S TATE (24)
4.4 PCI B3S TATE - O FF (25)
4.5 PCI B US P OWER S TATE T RANSITIONS (25)
警语4.6 PCI C LOCKING C ONSIDERATIONS (26)
4.6.1 Special Considerations for 66 MHz PCI Designs (26)
endesa4.7 C ONTROL/S TATUS OF PCI B US P OWER M ANAGEMENT S TATES (27)
4.7.1 Control of Secondary Bus Power Source and Clock (27)
5. PCI FUNCTION POWER MANAGEMENT STATES (29)
5.1 PCI F UNCTION D0S TATE (29)
5.2 PCI F UNCTION D1S TATE (29)
5.3 PCI F UNCTION D2S TATE (30)
5.4 PCI F UNCTION D3S TATE (30)
5.4.1 Software Accessible D3 (D3hot) (30)
5.4.2 Power Off (D3cold) (31)
5.5 PCI F UNCTION P OWER S TATE T RANSITIONS (31)
5.6 PCI F UNCTION P OWER M ANAGEMENT P OLICIES (33)
5.6.1 State Transition Recovery Time Requirements (36)
6. PCI BRIDGES AND POWER MANAGEMENT (38)
6.1 H OST B RIDGE, OR OTHER M OTHERBOARD E NUMERATED B RIDGE (40)
6.2 PCI TO PCI B RIDGES (40)
6.3 PCI TO C ARDBUS B RIDGE (40)
7. POWER MANAGEMENT EVENTS (41)
7.1 P OWER M ANAGEMENT E VENT (PME#) R OUTING (44)
P OWER M ANAGEMENT E VENTS (45)aggressive翻译
7.2 A UXILIARY P OWER FOR D3
COLD
8. SOFTWARE SUPPORT FOR PCI POWER MANAGEMENT (46)
8.1 I DENTIFYING P CI F UNCTION C APABILITIES (46)
8.2 P LACING PCI F UNCTIONS IN A LOW POWER STATE (46)
8.2.1 Bus (47)
8.2.2 D3 State (47)
8.3 R ESTORING PCI F UNCTIONS FROM A LOW POWER STATE (47)
8.3.1 D0 “Uninitialized” and the DSI Bit (47)
8.3.2 D1 and D2 States (48)
8.3.3 D3 State (48)
8.4 W AKE EVENTS (48)
8.4.1 Wake Event Support (48)
8.4.2 The D0 “Initialized” State From a Wake Event (49)
8.5 G ET CAPABILITIES (49)
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8.6 S ET P OWER S TATE (49)
8.7 G ET P OWER S TATUS (49)
8.8 S YSTEM BIOS I NITIALIZATION (50)
9. OTHER CONSIDERATIONS (51)
Tables
T ABLE 1. PCI S TATUS R EGISTER (12)
T ABLE 2. C APABILITIES P OINTER - C AP_P TR (12)
T ABLE 3. PCI C ONFIGURATION S PACE H EADER T YPE / C AP_P TR MAPPINGS (13)
闪烁的意思T ABLE 4. C APABILITY I DENTIFIER - C AP_ID (14)
T ABLE 5. N EXT I TEM P OINTER - N EXT_I TEM_P TR (15)
T ABLE 6. P OWER M ANAGEMENT C APABILITIES - PMC (15)
T ABLE 7. P OWER M ANAGEMENT C ONTROL/S TATUS - PMCSR (17)
T ABLE 8. PMCSR B RIDGE S UPPORT E XTENSIONS - PMCSR_BSE (19)
T ABLE 9. D ATA R EGISTER (20)
T ABLE 10. P OWER C ONSUMPTION/D ISSIPATION R EPORTING (21)
T ABLE 11. PCI B US P OWER M ANAGEMENT S TATES (23)
T ABLE 12. PCI B US P OWER AND C LOCK C ONTROL (27)
T ABLE 13. D0 P OWER M ANAGEMENT P OLICIES (34)
T ABLE 14. D1 P OWER M ANAGEMENT P OLICIES (34)
T ABLE 15. D2 P OWER M ANAGEMENT P OLICIES (35)
P OWER M ANAGEMENT P OLICIES (35)
T ABLE 16. D3
HOT
T ABLE 17. D3
P OWER M ANAGEMENT P OLICIES (36)
COLD
T ABLE 18. PCI F UNCTION S TATE T RANSITION D ELAYS (37)
T ABLE 19. PCI B RIDGE P OWER M ANAGEMENT P OLICIES (39)
