Freescale Semiconductor
Application Note
Embedded systems that utilize double data rate memory (DDR) can realize incread performance over traditional single data rate (SDR) memories. As the name implies, DDR enables two data transactions to occur within a single clock cycle without having to double the applied clock or without having to double the size of the data bus. This incread data bus performance is achieved by the introduction of source-synchronous data strobes that permit data to be captured on both the falling and rising edges of the strobe. Although DDR can bring improved performance to an embedded design, care must be obrved in the schematic and layout phas to ensure that desired performance is realized. Smaller tup and hold times, cleaner reference voltages, tighter trace matching, new I/O (SSTL-2) signaling, and the need for proper termination can prent the board designer with a new t of challenges that were not prent for SDR designs.
Document Number:AN2582
Rev. 4, 10/2005
Contents
1.SSTL-2 and Termination . . . . . . . . . . . . . . . . . . . . . . 2
2.DDR Signal Groupings . . . . . . . . . . . . . . . . . . . . . . . . 4
3.Controller Signal Pin-Out . . . . . . . . . . . . . . . . . . . . . . 5
4.General Comments About Board Stack-Up . . . . . . . . 6
5.Layout Order for the DDR Signal Groups . . . . . . . . . 6
6.Length Matching Overview . . . . . . . . . . . . . . . . . . . . 7
jedward7.General Layout Guidelines for the Signal Groups . . . 8
8.Additional Layout Guidelines for Specific
Implementations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
9.Logic Analyzer Support Packages . . . . . . . . . . . . . . 29
10.Interface Timing Analysis and Other Considerations 30
11.Improving Eye Diagrams . . . . . . . . . . . . . . . . . . . . . 43
12.Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
13.DDR Designer’s Checklist . . . . . . . . . . . . . . . . . . . . 46
英文手机铃声14.Other Uful References . . . . . . . . . . . . . . . . . . . . . . 48
15.Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Hardware and Layout Design Considerations for DDR Memory Interfaces by DSD Applications
Freescale Semiconductor, Inc.
Austin, TX
SSTL-2 and Termination
stormwindDesign challenges confronting the board designer can be summarized as follows:
•Routing requirements
•Power supply and decoupling, which includes the DDR devices and controller, the termination rail generation (V TT), and reference generation (V REF)
•Proper termination for a given memory topology
This application note provides the board designer with a number of layout considerations within the areas, and includes general recommendations that can rve as an initial baline for board designers as they begin specific implementation.
Specific implementations may consist of the following:
•Single or multi-DIMM—registered, unbuffered
•Single or multi SO-DIMM—registered, unbuffered
•Soldered-down discrete implementation
•Mixture—discretes plus DIMM expansion slots
Besides memory, composite memory topologies may also include on-board logic analyzer connections and expansion DIMM cards with analyzer connections.
The design guidelines in this document are applicable for PowerQUICC™ products that leverage the DDR IP core, and are bad on a compilation of internal platforms designed by Freescale. The guidelines were constructed to minimize board-related issues across multiple memory topologies while allowing maximum flexibility for the board designer.
Becau numerous memory topologies and interface frequencies are possible on the DDR interface, Freescale highly recommends that the board designer, through simulation, should verify all aspects (signal integrity, electrical timings, and so on) before PCB fabrication.
NOTE
Freescale recommends that when using this document the designer should
also consult the latest errata for additional items that may need
consideration.
Secondly, any specific AC timing parameters ud within this document are
ud for reference purpos only. The designer should consult the official
forget的用法
AC specifications for a given product.
1SSTL-2 and Termination
For DDR-I memories, JEDEC created and adopted a low voltage, high-speed signaling standard called ‘ries stub termination logic’ (SSTL). SSTL leverages an active motherboard termination scheme and overcomes the signal integrity concerns with legacy LVTTL signaling. As the name implies, SSTL is suited for u in mainstream memory interfaces where stubs and connectors are prent. The 2.5-V version, named SSTL-2, is prominent with DDR-I memories and is defined within JESD8-9B. The memory controller’s drivers and receivers are compatible.with SSTL-2.
The most common SSTL termination is the Class II single and parallel termination scheme shown in Figure1. This scheme involves using one ries resistor (R S) from the controller to the memory and one
SSTL-2 and Termination
termination resistor (R T ) attached to the termination rail (V TT ). This de facto approach is ud in commodity PC motherboard designs.
卤素NOTE
It is assumed in this document that the designer is using the mainstream termination found in commodity PC motherboards. Conquently, differing termination techniques can be valid and uful, but the designer should u simulation to validate this determination.
Figure 1. Typical Memory Interface Using Class II Option
NOTE
V alues for R S and R T are system-dependent and should be derived by board simulation. See Section 12, “Simulation,” for a list of potential termination ranges.
In a typical memory topology, the ries damping resistor (R S ), if ud, is placed away from the controller. This approach has two distinct advantages. Obviously, precious board space around the memory controller is freed, avoiding layout congestion and burdensome fan-out. Furthermore, this approach optimizes the signal integrity for the signals being nt from the controller to the memories, where more signals (addr + cmd) must be reliably received by multiple devices.
To realize the incread signaling frequencies, SSTL leverages high-gain differential receivers that a
re biad around a reference voltage denoted as V REF . Using the high-gain receivers allows a smaller voltage swing, reducing signal reflections, lowering EMI, improving ttling time, and yielding higher possible clock rates than possible with LVTTL signaling.
Figure 2 shows the SSTL interface levels. The AC logic levels are the points at the receiver where the AC input timing parameters (tup and hold) must be satisfied. The DC logic levels provide a point of
niddhysteresis. When the input level has crosd the DC reference point, the receiver switches to the new logic level and maintains this new state as long as the signal does not cross below the threshold. Conquently, SSTL bus are less susceptible to overshoot, undershoot, and ringing effects.
Driver
Receiver
R T
R S
V TT
V REF
V IN
V IN
DDR Signal Groupings
Figure 2. SSTL Signaling
1.1Termination Dissipation
Sink and source currents flow through R S and R T . Assuming worst-ca parameters and that the Class II termination scheme of Figure 1 is ud, the power dissipation for the resistors is as follows:
P (RT and RS) = I 2 * R = (26.5 mA)2 * (25 Ω) = 17.6 mW.
NOTE
See Section 7.8, “DDR VTT V oltage Rail,” for current calculations.
Small compact 4-pin resistor packages (16mm ×32mm) that provide dissipation up to 1/16Watt (62.5mW) are available. Such devices are ideal for the DDR termination.
2DDR Signal Groupings
高贵的意思The DDR memory controller consists of more than 130 signals and provides a glueless interface for the memory subsystem. The signals can be divided into the following signal groups for the purpo of this design guide:•Clocks •Data
•Address/Command •Control
•Feedback signals
V DD Q (2.3 V Minimum)V OH (MIN)1.560 V
1.400 V 1.300 V 1.275 V 1.250 V 1.225 V 1.200 V 1.100 V
0.940 V V OL (MAX)V SS Q
V IH
AC V REF + AC Noi V REF + DC Error V REF – DC Error V REF – AC Noi V IH
DC
V IL
AC
V IL
DC Note that numbers are nominal, utilizing R S = R T = 25 Ω.
Transmitter
eminem新专辑Receiver
Controller Signal Pin-Out
Table 1 depicts signal groupings for the DDR interface. The remaining ctions of this document describe further details about PCB layout recommendations for each of the groups.
3Controller Signal Pin-Out
The pin-out for the DDR interface facilitates ea of routing to a standard JEDEC DIMM connector. For non-DIMM topologies (that is, discretes), DDR devices should be placed in a analogous fashion to optimize signal fan-out.
Table 1. DDR Signal Groupings for Routing Purpos
Group
Signal Name Description
Section
Clocks
MCK[0:5]DDR differential clock outputs See Section 7.1, “Clock Signal Group MCK[0:5] and MCK[0:5]”
MCK[0:5]
DDR differential clock outputs (complement)Datacrush on you
MDQ[0:63]64-bit data bus See Section 7.2, “Data—MDQ[0:63], MDQS[0:8], MDM[0:8], MECC[0:7]”
MECC[0:7]ECC pins MDM[0:8]Data mask pins MDQS[0:8]
Data strobe pins Address/Command
MA[0:14]Address bus See Section 7.3, “Address and Command Signal Group”
MBA[0:1]Bank address MRAS Row address strobe MCAS Column address strobe MWE
Write enable Control
MCKE[0:1]Clock enable See Section 7.4, “Control Signal Group”MCS[0:3]
Chip lects
Feedback
MSYNC_OUT DRAM DLL synchronization output See Section 7.5, “Feedback Signal Group”MSYNC_IN
DRAM DLL synchronization input Power
V REF Voltage reference for differential receivers
See Section 7.6, “DDR Power Delivery”V TT
Termination voltage
General Comments About Board Stack-Up
Figure 3 shows general DDR controller pin-out flow.
Figure 3. General DDR Controller Pin-Out Flow
NOTE
The figure shows generic topology if a ries damping (R S ) and parallel termination (R T ) scheme is ud.
4General Comments About Board Stack-Up
Freescale recommends placing all DDR signals on critical layers that are ground-referenced, which
ensures the lowest impedance for the return currents and provides improved signal integrity performance. Ground referencing is especially critical for the data group as it operates at the 2x clock rate.
If trade-offs must be made, allow the data and clock signal groups to be routed over solid ground planes and other DDR signal groups to be routed over solid power plans.
NOTE
When ground or power referencing, the reference must be solid and continuous from the BGA ball through the end termination. Wherever power plan referencing is ud, take care to avoid DDR signal cross that split power planes, which adverly affect the impedance of the return currents.
5Layout Order for the DDR Signal Groups
To help ensure that the DDR interface is properly optimized, Freescale recommends the following quence for routing the DDR memory channel:
无所事事的海盗
1.Power (V TT island with termination resistors, V REF )
DDR PowerQUICC
DIMM0
DIMM1V TT Island
Segment A
Segment B Segment C
Region
