MK2069-01
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VCXO-Bad Line Card Clock Synchronizer
Description
The MK2069-01 is a VCXO (Voltage Controlled Crystal
Oscillator) bad clock generator that offers system
synchronization, jitter attenuation, and frequency
multiplication or translation. It can accept an unstable,
jittery input clock and provide a de-jittered, low pha
noi output clock at a ur determined frequency. The
device’s clock multiplication ratios are ur lectable
since all major PLL divider blocks can be configured
through device pin ttings. External PLL loop filter
components allow tailoring of the VCXO PLL loop
respon and therefore the clock jitter attenuation
characteristics.
The MK2069-01 is ideal for line card applications. Its
three input MUX enables lection of the master or
slave (backup) system clocks, as well as a backup local
line card clock. The lock detector (LD) output rves as
a clock status monitor. The clear (CLR) input enables
rapid synchronization to the pha of a newly lected
input clock, while eliminating the generation of extra
clock cycles and wander caud by memory in the PLL纠缠不休
交通拥挤 英语
feedback divider. CLR also rves as a temporary
holdover function when kept low.
Features
•Input clock frequency of 1kHz to 170MHz
•Output clock frequency of 500kHz to 160MHz
•Jitter attenuation of input clock provided by VCXO
circuit. Jitter transfer characteristics ur configured
through lection of external loop filter components.
•3:1 Input MUX for input reference clocks
•PLL lock status output
•PLL Clear function allows amless synchronizing to
an altered input clock pha, virtually eliminating the
generation of wander or extra clock cycles.
•VCXO-bad clock generation offers very low jitter
and pha noi generation, even with a low
frequency or jittery input clock.
•2nd PLL provides translation of VCXO PLL output
(VCLK) to higher or alternate clock frequencies
(TCLK).
•Device will free-run in the abnce of an input clock
bad on the VCXO crystal frequency.
•56 pin TSSOP package
•Single 3.3V power supply
•5V tolerant inputs on ICLK0 and ICLK1
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Block Diagram
Pin Assignment
Input Selection Tables
Input Mux Selection Table
VCXO PLL Reference Divider Selection Table
VCXO PLL Feedback Divider Selection
VCXO PLL Scaling Divider Selection Table
Translator PLL Reference Divider Selection
Table
Translator PLL Feedback Divider Selection
Translator PLL Scaling Divider Selection Table
MX1MX0Input Selection
00ICLK001ICLK010ICLK111
ICLK2
RV1RV0RV Divider Ratio
0040112810211
1
FV11:0FV Divider Ratio Notes 0 (002)
For FV address 0 to 4094,FV Divide = Address + 20 (013)
::
<1040961 (111)
SV2SV1SV0SV Divider Ratio
0004001601080111010012101211016111
1
RT1RT0RT Divider Ratio
00201310411
1
FT5:0FT Divider Ratio Notes
0000002For FT address 0 to 62,FT Divide = Address + 2
000001
3::11111064111111
1
ST1ST0ST Divider Ratio
00201410811
16
Pin Descriptions
Pin Number
Pin Name
Pin Type
Pin Description
1ST0Input Scaling Divider bit 0 input, T ranslator PLL (internal pull-up).2ST1Input Scaling Divider bit 1 input, T ranslator PLL (internal pull-up).3RT0Input Reference Divider bit 0 input, Translator PLL (internal pull-up).4RT1Input Reference Divider bit 1 input, Translator PLL (internal pull-up).5FT0Input Feedback Divider bit 0 input, Translator PLL (internal pull-up).6FT1Input Feedback Divider bit 1 input, Translator PLL (internal pull-up).7FT2Input Feedback Divider bit 2 input, Translator PLL (internal pull-up).8FT3Input Feedback Divider bit 3 input, Translator PLL (internal pull-up).9FT4Input Feedback Divider bit 4 input, Translator PLL (internal pull-up).10FT5Input Feedback Divider bit 5 input, Translator PLL (internal pull-up).11RV0Input Reference Divider bit 0 input, VCXO PLL (internal pull-up).12VDDT Power Power Supply connection for translator PLL.13GNDT Ground Ground connection for translator PLL.
14X1-Crystal oscillator input. Connect this pin to the external reference crystal.15VDDV Power Power Supply connection for VCXO PLL.
16X2-Crystal oscillator output. Connect this pin to the external reference crystal.17GNDV Ground Ground connection for VCXO PLL.
18LFR -Loop filter connection, reference node. Refer to loop filter circuit on page 6.19LF -Loop filter connection, active node. Refer to loop filter circuit on page 6.20ISET -Charge pump current tting input. Refer to loop filter circuit on page 6.21FV0Input Feedback Divider bit 0 input, VCXO PLL (internal pull-up).22FV1Input Feedback Divider bit 1 input, VCXO PLL (internal pull-up).23FV2Input Feedback Divider bit 2 input, VCXO PLL (internal pull-up).24FV3Input Feedback Divider bit 3 input, VCXO PLL (internal pull-up).25FV4Input Feedback Divider bit 4 input, VCXO PLL (internal pull-up).26FV5Input Feedback Divider bit 5 input, VCXO PLL (internal pull-up).27FV6Input Feedback Divider bit 6 input, VCXO PLL (internal pull-up).28FV7Input Feedback Divider bit 7 input, VCXO PLL (internal pull-up).29FV8Input Feedback Divider bit 8 input, VCXO PLL (internal pull-up).30FV9Input Feedback Divider bit 9 input, VCXO PLL (internal pull-up).31FV10Input Feedback Divider bit 10 input, VCXO PLL (internal pull-up).32FV11Input Feedback Divider bit 11 input, VCXO PLL (internal pull-up).33MX1Input Input MUX lection bit 1 (internal pull-up).34ICLK2Input Reference clock input
2.
35ICLK0Input Reference clock input 0. 5V tolerant input.
36CLR Input Clear input, clears VCXO PLL dividers when low (internal pull-up).
37LDC -Lock detector threshold tting circuit connection. Refer to circuit on page 10. 38GND Ground
Digital ground connection.
39LDR -Lock detector threshold tting circuit connection. Refer to circuit on page 10. 40RCLK Output VCXO PLL pha detector Reference Clock output.
41
GNDP
Ground
Ground connection for output drivers (VCLK, TCLK, RCLK, LD, LDR).
Functional Description
The MK2069-01 is a PLL (pha locked loop) bad clock generator that generates output clocks
synchronized to an input reference clock. It contains two cascaded PLL ’s with ur lectable divider ratios.The first PLL is VCXO-bad and us an external pullable crystal as part of the normal “VCO” (voltage controlled oscillator) function of the PLL. The u of a VCXO assures a low pha noi clock source even when a low PLL loop bandwidth is implemented. A low loop bandwidth is needed when the input reference frequency is low, or when jitter attenuation of the input reference is desired.
The cond PLL is ud to translate or multiply the frequency of the VCXO PLL which has a maximum output frequency of 27 MHz. This cond PLL, or Translator PLL, us an on-chip VCO circuit that can provide an output clock up to 160 MHz. The Translator PLL us a high loop bandwidth (typically greater than 1 MHz) to assure stability of the VCO clock output. It requires a stable, high frequency input reference which is provided by the VCXO PLL.
The divide values of the divider blocks within both PLLs are t by device pin configuration. This enables the system designer to define the following:
emt•Input clock frequency •VCXO crystal frequency •VCLK output frequency
•RCLK output frequency, which is also the pha detector frequency of the VCXO PLL.•
TCLK output frequency
Any unud clock or logic outputs can be tri-stated to reduce interference (jitter, pha noi) on other clock outputs. Outputs can also be tri-stated for system testing purpos.
External components are ud to configure the VCXO PLL loop respon. This rves to maximize loop stability and to achieve the desired input clock jitter attenuation characteristics.
42VCLK Output Clock output from VCXO PLL
43VDDP Power Power Supply connection for output drivers (VCLK, TCLK, RCLK, LD, LDR).44TCLK Output Clock output from Translator PLL
45LD Output Lock detector output.
46VDD Power Power Supply connection for digital circuitry.
47OER Input Output enable for RCLK. RCLK is tri-stated when low (internal pull-up).48OEV Input Output enable for VCLK. VCLK is tri-stated when low (internal pull-up).
49OET Input Output enable for TCLK. TCLK is tri-stated and the translator PLL is disabled when low (internal pull-up).
50OEL Input Output enable for LD and LDR. Both are tri-stated when low (internal pull-up).51ICLK1Input Reference clock input 1. 5V tolerant input.
52MX0Input Input MUX lection bit 0 input (internal pull-up).
53RV1Input Reference Divider bit 1 input, VCXO PLL (internal pull-up).54SV0Input Scaler Divider bit 0 input, VCXO PLL (internal pull-up).55SV1Input Scaler Divider bit 1 input, VCXO PLL (internal pull-up).56
SV2
Input
Scaler Divider bit 2 input, VCXO PLL (internal pull-up).
Pin Number
durangoPin Name
Pin Type
Pin Description
Application Information
The MK2069-01 is a mixed analog / digital integrated circuit that is nsitive to PCB (printed circuit board) layout and external component lection. Ud properly, the device will provide the same high performance expected from a canned VCXO-bad hybrid timing device, but at a lower cost. To help avoid unexpected problems, the guidance provided in the ctions below should be followed.
引道Setting VCLK Output Frequency
The frequency of the VCLK output is determined by the following relationship:
Where:
FV Divider = 1 to 4096
RV Divider = 1,2,4 or 128
The operational frequency range of VCLK is t by the allowable frequency range of the external VCXO crystal and by the internal VCXO divider lections: Where:
F(VCXO) = F(External Crystal) = 8 to 27 MHz
SV Divider = 1,2,4,6,8,10,12 or 16
A higher crystal frequency will generally produce lower pha noi and therefore is preferred. A crystal frequency between 13.5 MHz and 27 MHz is recommended.
Becau VCLK is generated by the external crystal, the frequency range of VCLK in a given configuration is limited to the pullable range of the crystal. This is guaranteed to be +/-115 ppm minimum. This frequency range in ppm also applies to the input clock and other clock outputs if the device is to remain frequency locked to the input, which is required for normal operation.Setting TCLK Output Frequency
The clock frequency of TCLK is determined by: Where:
FT Divider = 1 to 64
RT Divider = 1 to 4
The frequency range of TCLK is t by the operational range of the internal VCO circuit and the output divider lections:
Where:
aloft
f(VCO) = 40 to 320 MHz
ST Divider = 2,4,8 or 16
A higher VCO frequency will generally produce lower pha noi and therefore is preferred.
MK2069-01 Loop Respon and JItter
Attenuation Characteristics我的天啊英文
The MK2069-01 will reduce the transfer of pha jitter existing on the input reference clock to the output clock. This operation is known as jitter attenuation. The
low-pass frequency respon of the VCXO PLL loop is the mechanism that provides input jitter attenuation. Clock jitter, more accurately called pha jitter, is the overall instability of the clock period which can be measured in the time domain using an oscilloscope, for instance. Jitter is comprid of pha noi which can be reprented in the frequency domain. The pha noi of the input reference clock is attenuated according to the VCXO PLL low-pass frequency respon curve. The respon curve, and thus the jitter attenuation characteristics, can be established through the lection of external MK2069-01 passive components and other device tting as explained in th
e following ction.
f(VCLK)
FV Divider
RV Divider
----------------------------f(ICLK)
×
=
f(VCLK)
f VCXO
()
SV Divider
-
----------------------
=
f(TCLK)
FT Divider
RT Divider
---------------------------f(VCLK)
×
=
f(TCLK)
f(VC0)
ST Divider
-
---------------------
=
Setting the VCXO PLL Loop Respon. The VCXO PLL loop respon is determined both by fixed device characteristics and by other characterizes t by the ur. This includes the values of R S, C S, C P and R SET as shown in the External VCXO PLL Components figure on this page.
The VCXO PLL loop bandwidth is approximated by: Where:
R S = Value of resistor R S in loop filter in Ohms
I CP = Charge pump current in amps
(e table on page 7)
K O = VCXO Gain in Hz/V
(e table on page 8)
SV Divider = 1,2,4,6,8,10,12 or 16
FV Divider = 1 to 4096
The above equation calculates the “normalized” loop bandwidth (denoted as “NBW”) which is approx
imately equal to the - 3dB bandwidth. NBW does not take into account the effects of damping factor or the cond pole impod by C P. It does, however, provide a uful approximation of filter performance.
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To prevent jitter on VCLK due to modulation of the VCXO PLL by the pha detector frequency, the following general rule should be obrved:
.
The PLL loop damping factor is determined by:
Where:
C S = Value of capacitor C S in loop filter in
Farads External VCXO PLL Components
In general, the loop damping factor should be 0.7 or greater to ensure output stability. A higher damping factor will create less peaking in the passband and will further ensure output stability with the prence of system and power supply noi. A damping factor of 4 will ensure a passband peak l
ess then 0.2dB which may be required for network clock wander transfer compliance. A higher damping factor may also increa output clock jitter when there is excess digital noi in the system application, due to the reduced ability of the PLL to respond to and therefore compensate for pha noi ingress.
Notes on tting the value of C P
As another general rule, the following relationship should be maintained between components C S and C P in the loop filter:
NBW(VCXO PLL)
R S I CP
×K
O
×
2πSV Divider
×FV Divider
×
--------------------------------------------------------------------------=
NBW(VCO PLL)
f(Pha Detector)
20
--------------------------------------≤
DF(VCLK)
R S
2
-----
I CP C S
×K
O
×
SV Divider FV Divider
×
--------------------------------------------------------------
×
=
C P
C S
20
-----
=
